/*
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* P1025 TWR Device Tree Source stub (no addresses or top-level ranges)
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/{
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aliases {
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ethernet3 = &enet3;
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ethernet4 = &enet4;
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};
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};
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&lbc {
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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/* This location must not be altered */
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/* 256KB for Vitesse 7385 Switch firmware */
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reg = <0x0 0x00040000>;
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label = "NOR Vitesse-7385 Firmware";
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read-only;
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};
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partition@40000 {
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/* 256KB for DTB Image */
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reg = <0x00040000 0x00040000>;
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label = "NOR DTB Image";
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};
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partition@80000 {
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/* 5.5 MB for Linux Kernel Image */
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reg = <0x00080000 0x00580000>;
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label = "NOR Linux Kernel Image";
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};
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partition@400000 {
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/* 56.75MB for Root file System */
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reg = <0x00600000 0x038c0000>;
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label = "NOR Root File System";
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};
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partition@ec0000 {
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/* This location must not be altered */
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/* 256KB for QE ucode firmware*/
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reg = <0x03ec0000 0x00040000>;
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label = "NOR QE microcode firmware";
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read-only;
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};
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partition@f00000 {
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/* This location must not be altered */
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/* 512KB for u-boot Bootloader Image */
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/* 512KB for u-boot Environment Variables */
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reg = <0x03f00000 0x00100000>;
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label = "NOR U-Boot Image";
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read-only;
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};
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};
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/* CS2 for Display */
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display@2,0 {
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compatible = "solomon,ssd1289fb";
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reg = <0x2 0x0000 0x0004>;
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};
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};
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&soc {
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usb@22000 {
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phy_type = "ulpi";
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};
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mdio@24000 {
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phy0: ethernet-phy@2 {
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interrupt-parent = <&mpic>;
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interrupts = <1 1 0 0>;
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reg = <0x2>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&mpic>;
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interrupts = <2 1 0 0>;
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reg = <0x1>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@25000 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@26000 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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ptp_clock@b0e00 {
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compatible = "fsl,etsec-ptp";
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reg = <0xb0e00 0xb0>;
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interrupts = <68 2 0 0 69 2 0 0>;
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fsl,tclk-period = <10>;
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fsl,tmr-prsc = <2>;
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fsl,tmr-add = <0xc0000021>;
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fsl,tmr-fiper1 = <999999990>;
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fsl,tmr-fiper2 = <99990>;
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fsl,max-adj = <133333332>;
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};
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enet0: ethernet@b0000 {
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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enet1: ethernet@b1000 {
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status = "disabled";
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};
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enet2: ethernet@b2000 {
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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par_io@e0100 {
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0xe0100 0x60>;
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ranges = <0x0 0xe0100 0x60>;
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device_type = "par_io";
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num-ports = <3>;
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pio1: ucc_pin@1 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
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0x0 0x17 0x2 0x0 0x2 0x0 /* CLK12 */
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0x0 0x18 0x2 0x0 0x1 0x0 /* CLK9 */
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0x0 0x7 0x1 0x0 0x2 0x0 /* ENET1_TXD0_SER1_TXD0 */
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0x0 0x9 0x1 0x0 0x2 0x0 /* ENET1_TXD1_SER1_TXD1 */
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0x0 0xb 0x1 0x0 0x2 0x0 /* ENET1_TXD2_SER1_TXD2 */
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0x0 0xc 0x1 0x0 0x2 0x0 /* ENET1_TXD3_SER1_TXD3 */
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0x0 0x6 0x2 0x0 0x2 0x0 /* ENET1_RXD0_SER1_RXD0 */
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0x0 0xa 0x2 0x0 0x2 0x0 /* ENET1_RXD1_SER1_RXD1 */
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0x0 0xe 0x2 0x0 0x2 0x0 /* ENET1_RXD2_SER1_RXD2 */
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0x0 0xf 0x2 0x0 0x2 0x0 /* ENET1_RXD3_SER1_RXD3 */
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0x0 0x5 0x1 0x0 0x2 0x0 /* ENET1_TX_EN_SER1_RTS_B */
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0x0 0xd 0x1 0x0 0x2 0x0 /* ENET1_TX_ER */
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0x0 0x4 0x2 0x0 0x2 0x0 /* ENET1_RX_DV_SER1_CTS_B */
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0x0 0x8 0x2 0x0 0x2 0x0 /* ENET1_RX_ER_SER1_CD_B */
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0x0 0x11 0x2 0x0 0x2 0x0 /* ENET1_CRS */
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0x0 0x10 0x2 0x0 0x2 0x0>; /* ENET1_COL */
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};
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pio2: ucc_pin@2 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x1 0x13 0x1 0x0 0x1 0x0 /* QE_MUX_MDC */
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0x1 0x14 0x3 0x0 0x1 0x0 /* QE_MUX_MDIO */
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0x1 0xb 0x2 0x0 0x1 0x0 /* CLK13 */
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0x1 0x7 0x1 0x0 0x2 0x0 /* ENET5_TXD0_SER5_TXD0 */
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0x1 0xa 0x1 0x0 0x2 0x0 /* ENET5_TXD1_SER5_TXD1 */
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0x1 0x6 0x2 0x0 0x2 0x0 /* ENET5_RXD0_SER5_RXD0 */
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0x1 0x9 0x2 0x0 0x2 0x0 /* ENET5_RXD1_SER5_RXD1 */
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0x1 0x5 0x1 0x0 0x2 0x0 /* ENET5_TX_EN_SER5_RTS_B */
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0x1 0x4 0x2 0x0 0x2 0x0 /* ENET5_RX_DV_SER5_CTS_B */
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0x1 0x8 0x2 0x0 0x2 0x0>; /* ENET5_RX_ER_SER5_CD_B */
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};
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pio3: ucc_pin@3 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x0 0x16 0x2 0x0 0x2 0x0 /* SER7_CD_B*/
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0x0 0x12 0x2 0x0 0x2 0x0 /* SER7_CTS_B*/
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0x0 0x13 0x1 0x0 0x2 0x0 /* SER7_RTS_B*/
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0x0 0x14 0x2 0x0 0x2 0x0 /* SER7_RXD0*/
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0x0 0x15 0x1 0x0 0x2 0x0>; /* SER7_TXD0*/
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};
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pio4: ucc_pin@4 {
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pio-map = <
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/* port pin dir open_drain assignment has_irq */
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0x1 0x0 0x2 0x0 0x2 0x0 /* SER3_CD_B*/
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0x0 0x1c 0x2 0x0 0x2 0x0 /* SER3_CTS_B*/
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0x0 0x1d 0x1 0x0 0x2 0x0 /* SER3_RTS_B*/
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0x0 0x1e 0x2 0x0 0x2 0x0 /* SER3_RXD0*/
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0x0 0x1f 0x1 0x0 0x2 0x0>; /* SER3_TXD0*/
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};
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};
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};
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&qe {
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enet3: ucc@2000 {
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device_type = "network";
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compatible = "ucc_geth";
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rx-clock-name = "clk12";
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tx-clock-name = "clk9";
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pio-handle = <&pio1>;
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phy-handle = <&qe_phy0>;
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phy-connection-type = "mii";
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};
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mdio@2120 {
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qe_phy0: ethernet-phy@18 {
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interrupt-parent = <&mpic>;
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interrupts = <4 1 0 0>;
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reg = <0x18>;
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device_type = "ethernet-phy";
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};
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qe_phy1: ethernet-phy@19 {
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interrupt-parent = <&mpic>;
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interrupts = <5 1 0 0>;
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reg = <0x19>;
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device_type = "ethernet-phy";
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};
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tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet4: ucc@2400 {
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device_type = "network";
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compatible = "ucc_geth";
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rx-clock-name = "none";
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tx-clock-name = "clk13";
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pio-handle = <&pio2>;
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phy-handle = <&qe_phy1>;
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phy-connection-type = "rmii";
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};
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serial2: ucc@2600 {
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device_type = "serial";
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compatible = "ucc_uart";
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port-number = <0>;
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rx-clock-name = "brg6";
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tx-clock-name = "brg6";
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pio-handle = <&pio3>;
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};
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serial3: ucc@2200 {
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device_type = "serial";
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compatible = "ucc_uart";
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port-number = <1>;
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rx-clock-name = "brg2";
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tx-clock-name = "brg2";
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pio-handle = <&pio4>;
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};
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};
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