// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC8641 HPCN Device Tree Source
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*
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* Copyright 2006 Freescale Semiconductor Inc.
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*/
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/include/ "mpc8641si-pre.dtsi"
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/ {
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model = "MPC8641HPCN";
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compatible = "fsl,mpc8641hpcn";
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memory {
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device_type = "memory";
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reg = <0x00000000 0x40000000>; // 1G at 0x0
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};
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lbc: localbus@ffe05000 {
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reg = <0xffe05000 0x1000>;
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ranges = <0 0 0xef800000 0x00800000
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2 0 0xffdf8000 0x00008000
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3 0 0xffdf0000 0x00008000>;
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flash@0,0 {
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compatible = "cfi-flash";
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reg = <0 0 0x00800000>;
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bank-width = <2>;
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device-width = <2>;
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "kernel";
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reg = <0x00000000 0x00300000>;
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};
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partition@300000 {
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label = "firmware b";
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reg = <0x00300000 0x00100000>;
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read-only;
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};
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partition@400000 {
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label = "fs";
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reg = <0x00400000 0x00300000>;
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};
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partition@700000 {
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label = "firmware a";
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reg = <0x00700000 0x00100000>;
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read-only;
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};
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};
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};
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soc: soc8641@ffe00000 {
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ranges = <0x00000000 0xffe00000 0x00100000>;
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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mdio@24520 {
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phy0: ethernet-phy@0 {
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interrupts = <10 1 0 0>;
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reg = <0>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <10 1 0 0>;
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reg = <1>;
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};
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phy2: ethernet-phy@2 {
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interrupts = <10 1 0 0>;
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reg = <2>;
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};
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phy3: ethernet-phy@3 {
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interrupts = <10 1 0 0>;
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reg = <3>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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mdio@25520 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet2: ethernet@26000 {
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tbi-handle = <&tbi2>;
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phy-handle = <&phy2>;
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phy-connection-type = "rgmii-id";
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};
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mdio@26520 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet3: ethernet@27000 {
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tbi-handle = <&tbi3>;
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phy-handle = <&phy3>;
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phy-connection-type = "rgmii-id";
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};
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mdio@27520 {
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tbi3: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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rmu: rmu@d3000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,srio-rmu";
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reg = <0xd3000 0x500>;
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ranges = <0x0 0xd3000 0x500>;
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message-unit@0 {
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compatible = "fsl,srio-msg-unit";
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reg = <0x0 0x100>;
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interrupts = <
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53 2 0 0 /* msg1_tx_irq */
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54 2 0 0>;/* msg1_rx_irq */
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};
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message-unit@100 {
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compatible = "fsl,srio-msg-unit";
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reg = <0x100 0x100>;
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interrupts = <
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55 2 0 0 /* msg2_tx_irq */
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56 2 0 0>;/* msg2_rx_irq */
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};
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doorbell-unit@400 {
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compatible = "fsl,srio-dbell-unit";
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reg = <0x400 0x80>;
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interrupts = <
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49 2 0 0 /* bell_outb_irq */
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50 2 0 0>;/* bell_inb_irq */
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};
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port-write-unit@4e0 {
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compatible = "fsl,srio-port-write-unit";
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reg = <0x4e0 0x20>;
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interrupts = <48 2 0 0>;
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};
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};
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};
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pci0: pcie@ffe08000 {
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reg = <0xffe08000 0x1000>;
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ranges = <0x02000000 0x0 0x80000000 0x80000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xffc00000 0x0 0x00010000>;
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interrupt-map-mask = <0xff00 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x11 func 0 - PCI slot 1 */
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0x8800 0 0 1 &mpic 2 1 0 0
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0x8800 0 0 2 &mpic 3 1 0 0
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0x8800 0 0 3 &mpic 4 1 0 0
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0x8800 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 1 - PCI slot 1 */
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0x8900 0 0 1 &mpic 2 1 0 0
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0x8900 0 0 2 &mpic 3 1 0 0
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0x8900 0 0 3 &mpic 4 1 0 0
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0x8900 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 2 - PCI slot 1 */
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0x8a00 0 0 1 &mpic 2 1 0 0
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0x8a00 0 0 2 &mpic 3 1 0 0
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0x8a00 0 0 3 &mpic 4 1 0 0
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0x8a00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 3 - PCI slot 1 */
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0x8b00 0 0 1 &mpic 2 1 0 0
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0x8b00 0 0 2 &mpic 3 1 0 0
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0x8b00 0 0 3 &mpic 4 1 0 0
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0x8b00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 4 - PCI slot 1 */
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0x8c00 0 0 1 &mpic 2 1 0 0
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0x8c00 0 0 2 &mpic 3 1 0 0
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0x8c00 0 0 3 &mpic 4 1 0 0
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0x8c00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 5 - PCI slot 1 */
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0x8d00 0 0 1 &mpic 2 1 0 0
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0x8d00 0 0 2 &mpic 3 1 0 0
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0x8d00 0 0 3 &mpic 4 1 0 0
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0x8d00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 6 - PCI slot 1 */
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0x8e00 0 0 1 &mpic 2 1 0 0
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0x8e00 0 0 2 &mpic 3 1 0 0
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0x8e00 0 0 3 &mpic 4 1 0 0
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0x8e00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x11 func 7 - PCI slot 1 */
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0x8f00 0 0 1 &mpic 2 1 0 0
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0x8f00 0 0 2 &mpic 3 1 0 0
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0x8f00 0 0 3 &mpic 4 1 0 0
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0x8f00 0 0 4 &mpic 1 1 0 0
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/* IDSEL 0x12 func 0 - PCI slot 2 */
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0x9000 0 0 1 &mpic 3 1 0 0
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0x9000 0 0 2 &mpic 4 1 0 0
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0x9000 0 0 3 &mpic 1 1 0 0
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0x9000 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 1 - PCI slot 2 */
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0x9100 0 0 1 &mpic 3 1 0 0
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0x9100 0 0 2 &mpic 4 1 0 0
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0x9100 0 0 3 &mpic 1 1 0 0
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0x9100 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 2 - PCI slot 2 */
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0x9200 0 0 1 &mpic 3 1 0 0
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0x9200 0 0 2 &mpic 4 1 0 0
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0x9200 0 0 3 &mpic 1 1 0 0
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0x9200 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 3 - PCI slot 2 */
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0x9300 0 0 1 &mpic 3 1 0 0
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0x9300 0 0 2 &mpic 4 1 0 0
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0x9300 0 0 3 &mpic 1 1 0 0
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0x9300 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 4 - PCI slot 2 */
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0x9400 0 0 1 &mpic 3 1 0 0
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0x9400 0 0 2 &mpic 4 1 0 0
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0x9400 0 0 3 &mpic 1 1 0 0
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0x9400 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 5 - PCI slot 2 */
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0x9500 0 0 1 &mpic 3 1 0 0
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0x9500 0 0 2 &mpic 4 1 0 0
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0x9500 0 0 3 &mpic 1 1 0 0
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0x9500 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 6 - PCI slot 2 */
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0x9600 0 0 1 &mpic 3 1 0 0
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0x9600 0 0 2 &mpic 4 1 0 0
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0x9600 0 0 3 &mpic 1 1 0 0
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0x9600 0 0 4 &mpic 2 1 0 0
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/* IDSEL 0x12 func 7 - PCI slot 2 */
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0x9700 0 0 1 &mpic 3 1 0 0
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0x9700 0 0 2 &mpic 4 1 0 0
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0x9700 0 0 3 &mpic 1 1 0 0
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0x9700 0 0 4 &mpic 2 1 0 0
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// IDSEL 0x1c USB
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0xe000 0 0 1 &i8259 12 2
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0xe100 0 0 2 &i8259 9 2
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0xe200 0 0 3 &i8259 10 2
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0xe300 0 0 4 &i8259 11 2
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// IDSEL 0x1d Audio
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0xe800 0 0 1 &i8259 6 2
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// IDSEL 0x1e Legacy
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0xf000 0 0 1 &i8259 7 2
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0xf100 0 0 1 &i8259 7 2
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// IDSEL 0x1f IDE/SATA
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0xf800 0 0 1 &i8259 14 2
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0xf900 0 0 1 &i8259 5 2
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>;
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pcie@0 {
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ranges = <0x02000000 0x0 0x80000000
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0x02000000 0x0 0x80000000
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0x0 0x20000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00010000>;
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uli1575@0 {
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reg = <0 0 0 0 0>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <0x02000000 0x0 0x80000000
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0x02000000 0x0 0x80000000
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0x0 0x20000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00010000>;
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isa@1e {
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device_type = "isa";
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <0xf000 0 0 0 0>;
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ranges = <1 0 0x01000000 0 0
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0x00001000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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reg = <1 0x20 2
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1 0xa0 2
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1 0x4d0 2>;
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interrupt-controller;
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device_type = "interrupt-controller";
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <9 2 0 0>;
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};
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i8042@60 {
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#size-cells = <0>;
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#address-cells = <1>;
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reg = <1 0x60 1 1 0x64 1>;
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interrupts = <1 3 12 3>;
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interrupt-parent = <&i8259>;
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keyboard@0 {
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reg = <0>;
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compatible = "pnpPNP,303";
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};
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mouse@1 {
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reg = <1>;
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compatible = "pnpPNP,f03";
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};
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};
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rtc@70 {
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compatible =
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"pnpPNP,b00";
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reg = <1 0x70 2>;
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};
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gpio@400 {
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reg = <1 0x400 0x80>;
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};
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};
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};
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};
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};
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pci1: pcie@ffe09000 {
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reg = <0xffe09000 0x1000>;
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ranges = <0x02000000 0x0 0xa0000000 0xa0000000 0x0 0x20000000
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0x01000000 0x0 0x00000000 0xffc10000 0x0 0x00010000>;
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pcie@0 {
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ranges = <0x02000000 0x0 0xa0000000
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0x02000000 0x0 0xa0000000
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0x0 0x20000000
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0x01000000 0x0 0x00000000
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0x01000000 0x0 0x00000000
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0x0 0x00010000>;
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};
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};
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/*
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* Only one of Rapid IO or PCI can be present due to HW limitations and
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* due to the fact that the 2 now share address space in the new memory
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* map. The most likely case is that we have PCI, so comment out the
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* rapidio node. Leave it here for reference.
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rapidio@ffec0000 {
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reg = <0xffec0000 0x11000>;
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compatible = "fsl,srio";
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interrupts = <48 2 0 0>;
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#address-cells = <2>;
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#size-cells = <2>;
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fsl,srio-rmu-handle = <&rmu>;
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ranges;
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port1 {
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#address-cells = <2>;
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#size-cells = <2>;
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cell-index = <1>;
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ranges = <0 0 0x80000000 0 0x20000000>;
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};
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};
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*/
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};
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/include/ "mpc8641si-post.dtsi"
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