// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* MPC8572 DS Core1 Device Tree Source in CAMP mode.
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*
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* In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
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* can be shared, all the other devices must be assigned to one core only.
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* This dts allows core1 to have l2, dma2, eth2, eth3, pci2, msi.
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*
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* Please note to add "-b 1" for core1's dts compiling.
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*
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* Copyright 2007-2009 Freescale Semiconductor Inc.
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*/
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/include/ "mpc8572ds.dts"
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/ {
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model = "fsl,MPC8572DS";
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compatible = "fsl,MPC8572DS", "fsl,MPC8572DS-CAMP";
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cpus {
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PowerPC,8572@0 {
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status = "disabled";
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};
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PowerPC,8572@1 {
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};
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};
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localbus@ffe05000 {
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status = "disabled";
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};
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soc8572@ffe00000 {
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ecm-law@0 {
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status = "disabled";
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};
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ecm@1000 {
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status = "disabled";
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};
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memory-controller@2000 {
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status = "disabled";
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};
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memory-controller@6000 {
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status = "disabled";
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};
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i2c@3000 {
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status = "disabled";
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};
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i2c@3100 {
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status = "disabled";
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};
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serial@4500 {
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status = "disabled";
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};
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gpio-controller@f000 {
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status = "disabled";
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};
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l2-cache-controller@20000 {
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cache-size = <0x80000>; // L2, 512K
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};
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dma@21300 {
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status = "disabled";
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};
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ethernet@24000 {
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status = "disabled";
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};
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ptp_clock@24e00 {
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status = "disabled";
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};
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ethernet@25000 {
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status = "disabled";
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};
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mdio@25520 {
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status = "disabled";
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};
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crypto@30000 {
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status = "disabled";
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};
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pic@40000 {
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protected-sources = <
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18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
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29 30 34 35 36 40 /* enet0 enet1 */
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24 25 20 21 22 23 /* pci0 pci1 dma1 */
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43 /* i2c */
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0x1 0x2 0x3 0x4 /* pci slot */
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0x9 0xa 0xb 0xc /* usb */
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0x6 0x7 0xe 0x5 /* Audio elgacy SATA */
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0xe0 0xe1 0xe2 0xe3 /* msi */
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>;
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};
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timer@41100 {
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status = "disabled";
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};
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msi@41600 {
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msi-available-ranges = <0x80 0x80>;
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interrupts = <
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0xe4 0 0 0
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0xe5 0 0 0
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0xe6 0 0 0
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0xe7 0 0 0>;
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};
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global-utilities@e0000 {
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status = "disabled";
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};
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};
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pcie@ffe08000 {
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status = "disabled";
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};
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pcie@ffe09000 {
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status = "disabled";
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};
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};
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