/*
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* MPC8548CDS Device Tree Source stub (no addresses or top-level ranges)
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*
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* Copyright 2012 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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&board_lbc {
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x01000000>;
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bank-width = <2>;
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device-width = <2>;
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partition@0 {
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reg = <0x0 0x0b00000>;
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label = "ramdisk-nor";
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};
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partition@300000 {
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reg = <0x0b00000 0x0400000>;
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label = "kernel-nor";
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};
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partition@700000 {
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reg = <0x0f00000 0x060000>;
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label = "dtb-nor";
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};
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partition@760000 {
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reg = <0x0f60000 0x020000>;
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label = "env-nor";
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read-only;
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};
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partition@780000 {
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reg = <0x0f80000 0x080000>;
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label = "u-boot-nor";
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read-only;
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};
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};
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board-control@1,0 {
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compatible = "fsl,mpc8548cds-fpga";
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reg = <0x1 0x0 0x1000>;
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};
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};
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&board_soc {
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i2c@3000 {
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eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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};
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eeprom@56 {
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compatible = "atmel,24c64";
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reg = <0x56>;
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};
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eeprom@57 {
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compatible = "atmel,24c64";
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reg = <0x57>;
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};
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};
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i2c@3100 {
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eeprom@50 {
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compatible = "atmel,24c64";
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reg = <0x50>;
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};
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};
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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};
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mdio@24520 {
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phy0: ethernet-phy@0 {
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interrupts = <5 1 0 0>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <5 1 0 0>;
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reg = <0x1>;
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};
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phy2: ethernet-phy@2 {
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interrupts = <5 1 0 0>;
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reg = <0x2>;
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};
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phy3: ethernet-phy@3 {
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interrupts = <5 1 0 0>;
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reg = <0x3>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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};
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mdio@25520 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet2: ethernet@26000 {
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tbi-handle = <&tbi2>;
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phy-handle = <&phy2>;
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};
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mdio@26520 {
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tbi2: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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enet3: ethernet@27000 {
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tbi-handle = <&tbi3>;
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phy-handle = <&phy3>;
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};
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mdio@27520 {
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tbi3: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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};
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&board_pci0 {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x4 (PCIX Slot 2) */
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0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x5 (PCIX Slot 3) */
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0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
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0x2800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
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0x2800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
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0x2800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
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/* IDSEL 0x6 (PCIX Slot 4) */
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0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
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0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x8 (PCIX Slot 5) */
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0x4000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0x4000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0x4000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0x4000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0xC (Tsi310 bridge) */
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0x6000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0x6000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0x6000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0x6000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x14 (Slot 2) */
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0xa000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0xa000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0xa000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0xa000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x15 (Slot 3) */
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0xa800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
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0xa800 0x0 0x0 0x2 &mpic 0x2 0x1 0 0
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0xa800 0x0 0x0 0x3 &mpic 0x3 0x1 0 0
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0xa800 0x0 0x0 0x4 &mpic 0x0 0x1 0 0
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/* IDSEL 0x16 (Slot 4) */
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0xb000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0xb000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0xb000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
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0xb000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDSEL 0x18 (Slot 5) */
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0xc000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0xc000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0xc000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0xc000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x1C (Tsi310 bridge PCI primary) */
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0xe000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0xe000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0xe000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0xe000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0>;
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pci_bridge@1c {
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interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
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interrupt-map = <
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/* IDSEL 0x00 (PrPMC Site) */
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0000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x04 (VIA chip) */
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0x2000 0x0 0x0 0x1 &mpic 0x0 0x1 0 0
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0x2000 0x0 0x0 0x2 &mpic 0x1 0x1 0 0
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0x2000 0x0 0x0 0x3 &mpic 0x2 0x1 0 0
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0x2000 0x0 0x0 0x4 &mpic 0x3 0x1 0 0
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/* IDSEL 0x05 (8139) */
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0x2800 0x0 0x0 0x1 &mpic 0x1 0x1 0 0
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/* IDSEL 0x06 (Slot 6) */
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0x3000 0x0 0x0 0x1 &mpic 0x2 0x1 0 0
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0x3000 0x0 0x0 0x2 &mpic 0x3 0x1 0 0
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0x3000 0x0 0x0 0x3 &mpic 0x0 0x1 0 0
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0x3000 0x0 0x0 0x4 &mpic 0x1 0x1 0 0
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/* IDESL 0x07 (Slot 7) */
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0x3800 0x0 0x0 0x1 &mpic 0x3 0x1 0 0
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0x3800 0x0 0x0 0x2 &mpic 0x0 0x1 0 0
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0x3800 0x0 0x0 0x3 &mpic 0x1 0x1 0 0
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0x3800 0x0 0x0 0x4 &mpic 0x2 0x1 0 0>;
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reg = <0xe000 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x80000>;
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clock-frequency = <33333333>;
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isa@4 {
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device_type = "isa";
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#interrupt-cells = <2>;
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#size-cells = <1>;
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#address-cells = <2>;
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reg = <0x2000 0x0 0x0 0x0 0x0>;
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ranges = <0x1 0x0 0x1000000 0x0 0x0 0x1000>;
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interrupt-parent = <&i8259>;
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i8259: interrupt-controller@20 {
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interrupt-controller;
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device_type = "interrupt-controller";
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reg = <0x1 0x20 0x2
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0x1 0xa0 0x2
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0x1 0x4d0 0x2>;
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#address-cells = <0>;
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#interrupt-cells = <2>;
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compatible = "chrp,iic";
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interrupts = <0 1 0 0>;
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interrupt-parent = <&mpic>;
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};
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rtc@70 {
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compatible = "pnpPNP,b00";
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reg = <0x1 0x70 0x2>;
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};
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};
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};
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};
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