// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* GE IMP3A Device Tree Source
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*
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* Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
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*
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* Based on: P2020 DS Device Tree Source
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* Copyright 2009 Freescale Semiconductor Inc.
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*/
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/include/ "p2020si-pre.dtsi"
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/ {
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model = "GE_IMP3A";
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compatible = "ge,imp3a";
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memory {
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device_type = "memory";
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};
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lbc: localbus@fef05000 {
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reg = <0 0xfef05000 0 0x1000>;
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ranges = <0x0 0x0 0x0 0xff000000 0x01000000
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0x1 0x0 0x0 0xe0000000 0x08000000
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0x2 0x0 0x0 0xe8000000 0x08000000
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0x3 0x0 0x0 0xfc100000 0x00020000
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0x4 0x0 0x0 0xfc000000 0x00008000
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0x5 0x0 0x0 0xfc008000 0x00008000
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0x6 0x0 0x0 0xfee00000 0x00040000
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0x7 0x0 0x0 0xfee80000 0x00040000>;
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/* nor@0,0 is a mirror of part of the memory in nor@1,0
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
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reg = <0x0 0x0 0x1000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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label = "firmware";
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reg = <0x0 0x1000000>;
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read-only;
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};
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};
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*/
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nor@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ge,imp3a-paged-flash", "cfi-flash";
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reg = <0x1 0x0 0x8000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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label = "user";
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reg = <0x0 0x7800000>;
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};
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partition@7800000 {
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label = "firmware";
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reg = <0x7800000 0x800000>;
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read-only;
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};
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};
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nvram@3,0 {
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device_type = "nvram";
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compatible = "simtek,stk14ca8";
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reg = <0x3 0x0 0x20000>;
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};
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fpga@4,0 {
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compatible = "ge,imp3a-fpga-regs";
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reg = <0x4 0x0 0x20>;
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};
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gef_pic: pic@4,20 {
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#interrupt-cells = <1>;
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interrupt-controller;
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device_type = "interrupt-controller";
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compatible = "ge,imp3a-fpga-pic", "gef,fpga-pic-1.00";
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reg = <0x4 0x20 0x20>;
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interrupts = <6 7 0 0>;
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};
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gef_gpio: gpio@4,400 {
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#gpio-cells = <2>;
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compatible = "ge,imp3a-gpio";
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reg = <0x4 0x400 0x24>;
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gpio-controller;
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};
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wdt@4,800 {
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compatible = "ge,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
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"gef,fpga-wdt";
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reg = <0x4 0x800 0x8>;
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interrupts = <10 4>;
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interrupt-parent = <&gef_pic>;
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};
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/* Second watchdog available, driver currently supports one.
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wdt@4,808 {
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compatible = "gef,imp3a-fpga-wdt", "gef,fpga-wdt-1.00",
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"gef,fpga-wdt";
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reg = <0x4 0x808 0x8>;
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interrupts = <9 4>;
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interrupt-parent = <&gef_pic>;
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};
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*/
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nand@6,0 {
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compatible = "fsl,elbc-fcm-nand";
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reg = <0x6 0x0 0x40000>;
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};
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nand@7,0 {
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compatible = "fsl,elbc-fcm-nand";
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reg = <0x7 0x0 0x40000>;
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};
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};
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soc: soc@fef00000 {
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ranges = <0x0 0 0xfef00000 0x100000>;
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i2c@3000 {
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hwmon@48 {
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compatible = "national,lm92";
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reg = <0x48>;
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};
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hwmon@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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rtc@51 {
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compatible = "epson,rx8581";
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reg = <0x51>;
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};
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eti@6b {
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compatible = "dallas,ds1682";
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reg = <0x6b>;
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};
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};
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usb@22000 {
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phy_type = "ulpi";
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dr_mode = "host";
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};
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mdio@24520 {
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phy0: ethernet-phy@0 {
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interrupt-parent = <&gef_pic>;
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interrupts = <0xc 0x4>;
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reg = <0x1>;
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};
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phy1: ethernet-phy@1 {
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interrupt-parent = <&gef_pic>;
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interrupts = <0xb 0x4>;
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reg = <0x2>;
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};
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tbi0: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@25520 {
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tbi1: tbi-phy@11 {
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reg = <0x11>;
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device_type = "tbi-phy";
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};
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};
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mdio@26520 {
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status = "disabled";
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};
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enet0: ethernet@24000 {
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tbi-handle = <&tbi0>;
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phy-handle = <&phy0>;
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phy-connection-type = "gmii";
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};
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enet1: ethernet@25000 {
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tbi-handle = <&tbi1>;
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phy-handle = <&phy1>;
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phy-connection-type = "gmii";
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};
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enet2: ethernet@26000 {
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status = "disabled";
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};
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};
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pci0: pcie@fef08000 {
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ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xfe020000 0x0 0x10000>;
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reg = <0 0xfef08000 0 0x1000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xc0000000
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0x2000000 0x0 0xc0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci1: pcie@fef09000 {
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reg = <0 0xfef09000 0 0x1000>;
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ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xfe010000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0xa0000000
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0x2000000 0x0 0xa0000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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pci2: pcie@fef0a000 {
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reg = <0 0xfef0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0 0xfe000000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x10000>;
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};
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};
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};
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/include/ "p2020si-post.dtsi"
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