/*
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* B4420 Silicon/SoC Device Tree Source (post include)
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*
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* Copyright 2012 - 2015 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* This software is provided by Freescale Semiconductor "as is" and any
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* express or implied warranties, including, but not limited to, the implied
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* warranties of merchantability and fitness for a particular purpose are
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* disclaimed. In no event shall Freescale Semiconductor be liable for any
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* direct, indirect, incidental, special, exemplary, or consequential damages
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* (including, but not limited to, procurement of substitute goods or services;
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* loss of use, data, or profits; or business interruption) however caused and
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* on any theory of liability, whether in contract, strict liability, or tort
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* (including negligence or otherwise) arising in any way out of the use of
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* this software, even if advised of the possibility of such damage.
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*/
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&bman_fbpr {
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compatible = "fsl,bman-fbpr";
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alloc-ranges = <0 0 0x10000 0>;
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};
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&qman_fqd {
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compatible = "fsl,qman-fqd";
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alloc-ranges = <0 0 0x10000 0>;
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};
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&qman_pfdr {
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compatible = "fsl,qman-pfdr";
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alloc-ranges = <0 0 0x10000 0>;
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};
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&ifc {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "fsl,ifc", "simple-bus";
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interrupts = <25 2 0 0>;
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};
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/* controller at 0x200000 */
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&pci0 {
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compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
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device_type = "pci";
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#size-cells = <2>;
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#address-cells = <3>;
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bus-range = <0x0 0xff>;
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interrupts = <20 2 0 0>;
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fsl,iommu-parent = <&pamu0>;
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pcie@0 {
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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device_type = "pci";
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reg = <0 0 0 0 0>;
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interrupts = <20 2 0 0>;
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interrupt-map-mask = <0xf800 0 0 7>;
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interrupt-map = <
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/* IDSEL 0x0 */
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0000 0 0 1 &mpic 40 1 0 0
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0000 0 0 2 &mpic 1 1 0 0
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0000 0 0 3 &mpic 2 1 0 0
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0000 0 0 4 &mpic 3 1 0 0
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>;
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};
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};
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&dcsr {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,dcsr", "simple-bus";
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dcsr-epu@0 {
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compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
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interrupts = <52 2 0 0
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84 2 0 0
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85 2 0 0
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94 2 0 0
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95 2 0 0>;
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reg = <0x0 0x1000>;
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};
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dcsr-npc {
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compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
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reg = <0x1000 0x1000 0x1002000 0x10000>;
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};
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dcsr-nxc@2000 {
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compatible = "fsl,dcsr-nxc";
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reg = <0x2000 0x1000>;
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};
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dcsr-corenet {
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compatible = "fsl,dcsr-corenet";
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reg = <0x8000 0x1000 0x1A000 0x1000>;
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};
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dcsr-dpaa@9000 {
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compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
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reg = <0x9000 0x1000>;
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};
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dcsr-ocn@11000 {
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compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
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reg = <0x11000 0x1000>;
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};
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dcsr-ddr@12000 {
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compatible = "fsl,dcsr-ddr";
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dev-handle = <&ddr1>;
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reg = <0x12000 0x1000>;
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};
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dcsr-nal@18000 {
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compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
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reg = <0x18000 0x1000>;
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};
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dcsr-rcpm@22000 {
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compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
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reg = <0x22000 0x1000>;
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};
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dcsr-snpc@30000 {
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compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
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reg = <0x30000 0x1000 0x1022000 0x10000>;
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};
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dcsr-snpc@31000 {
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compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
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reg = <0x31000 0x1000 0x1042000 0x10000>;
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};
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dcsr-cpu-sb-proxy@100000 {
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compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
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cpu-handle = <&cpu0>;
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reg = <0x100000 0x1000 0x101000 0x1000>;
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};
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};
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&bportals {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "simple-bus";
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bman-portal@0 {
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compatible = "fsl,bman-portal";
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reg = <0x0 0x4000>, <0x1000000 0x1000>;
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interrupts = <105 2 0 0>;
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};
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bman-portal@4000 {
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compatible = "fsl,bman-portal";
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reg = <0x4000 0x4000>, <0x1001000 0x1000>;
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interrupts = <107 2 0 0>;
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};
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bman-portal@8000 {
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compatible = "fsl,bman-portal";
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reg = <0x8000 0x4000>, <0x1002000 0x1000>;
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interrupts = <109 2 0 0>;
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};
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bman-portal@c000 {
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compatible = "fsl,bman-portal";
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reg = <0xc000 0x4000>, <0x1003000 0x1000>;
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interrupts = <111 2 0 0>;
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};
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bman-portal@10000 {
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compatible = "fsl,bman-portal";
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reg = <0x10000 0x4000>, <0x1004000 0x1000>;
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interrupts = <113 2 0 0>;
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};
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bman-portal@14000 {
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compatible = "fsl,bman-portal";
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reg = <0x14000 0x4000>, <0x1005000 0x1000>;
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interrupts = <115 2 0 0>;
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};
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bman-portal@18000 {
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compatible = "fsl,bman-portal";
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reg = <0x18000 0x4000>, <0x1006000 0x1000>;
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interrupts = <117 2 0 0>;
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};
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bman-portal@1c000 {
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compatible = "fsl,bman-portal";
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reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
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interrupts = <119 2 0 0>;
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};
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bman-portal@20000 {
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compatible = "fsl,bman-portal";
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reg = <0x20000 0x4000>, <0x1008000 0x1000>;
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interrupts = <121 2 0 0>;
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};
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bman-portal@24000 {
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compatible = "fsl,bman-portal";
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reg = <0x24000 0x4000>, <0x1009000 0x1000>;
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interrupts = <123 2 0 0>;
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};
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bman-portal@28000 {
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compatible = "fsl,bman-portal";
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reg = <0x28000 0x4000>, <0x100a000 0x1000>;
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interrupts = <125 2 0 0>;
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};
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bman-portal@2c000 {
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compatible = "fsl,bman-portal";
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reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
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interrupts = <127 2 0 0>;
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};
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bman-portal@30000 {
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compatible = "fsl,bman-portal";
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reg = <0x30000 0x4000>, <0x100c000 0x1000>;
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interrupts = <129 2 0 0>;
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};
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bman-portal@34000 {
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compatible = "fsl,bman-portal";
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reg = <0x34000 0x4000>, <0x100d000 0x1000>;
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interrupts = <131 2 0 0>;
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};
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};
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&qportals {
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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compatible = "simple-bus";
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qportal0: qman-portal@0 {
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compatible = "fsl,qman-portal";
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reg = <0x0 0x4000>, <0x1000000 0x1000>;
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interrupts = <104 0x2 0 0>;
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cell-index = <0x0>;
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};
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qportal1: qman-portal@4000 {
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compatible = "fsl,qman-portal";
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reg = <0x4000 0x4000>, <0x1001000 0x1000>;
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interrupts = <106 0x2 0 0>;
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cell-index = <0x1>;
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};
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qportal2: qman-portal@8000 {
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compatible = "fsl,qman-portal";
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reg = <0x8000 0x4000>, <0x1002000 0x1000>;
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interrupts = <108 0x2 0 0>;
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cell-index = <0x2>;
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};
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qportal3: qman-portal@c000 {
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compatible = "fsl,qman-portal";
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reg = <0xc000 0x4000>, <0x1003000 0x1000>;
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interrupts = <110 0x2 0 0>;
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cell-index = <0x3>;
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};
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qportal4: qman-portal@10000 {
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compatible = "fsl,qman-portal";
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reg = <0x10000 0x4000>, <0x1004000 0x1000>;
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interrupts = <112 0x2 0 0>;
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cell-index = <0x4>;
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};
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qportal5: qman-portal@14000 {
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compatible = "fsl,qman-portal";
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reg = <0x14000 0x4000>, <0x1005000 0x1000>;
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interrupts = <114 0x2 0 0>;
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cell-index = <0x5>;
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};
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qportal6: qman-portal@18000 {
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compatible = "fsl,qman-portal";
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reg = <0x18000 0x4000>, <0x1006000 0x1000>;
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interrupts = <116 0x2 0 0>;
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cell-index = <0x6>;
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};
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qportal7: qman-portal@1c000 {
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compatible = "fsl,qman-portal";
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reg = <0x1c000 0x4000>, <0x1007000 0x1000>;
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interrupts = <118 0x2 0 0>;
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cell-index = <0x7>;
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};
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qportal8: qman-portal@20000 {
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compatible = "fsl,qman-portal";
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reg = <0x20000 0x4000>, <0x1008000 0x1000>;
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interrupts = <120 0x2 0 0>;
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cell-index = <0x8>;
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};
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qportal9: qman-portal@24000 {
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compatible = "fsl,qman-portal";
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reg = <0x24000 0x4000>, <0x1009000 0x1000>;
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interrupts = <122 0x2 0 0>;
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cell-index = <0x9>;
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};
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qportal10: qman-portal@28000 {
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compatible = "fsl,qman-portal";
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reg = <0x28000 0x4000>, <0x100a000 0x1000>;
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interrupts = <124 0x2 0 0>;
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cell-index = <0xa>;
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};
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qportal11: qman-portal@2c000 {
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compatible = "fsl,qman-portal";
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reg = <0x2c000 0x4000>, <0x100b000 0x1000>;
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interrupts = <126 0x2 0 0>;
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cell-index = <0xb>;
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};
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qportal12: qman-portal@30000 {
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compatible = "fsl,qman-portal";
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reg = <0x30000 0x4000>, <0x100c000 0x1000>;
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interrupts = <128 0x2 0 0>;
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cell-index = <0xc>;
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};
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qportal13: qman-portal@34000 {
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compatible = "fsl,qman-portal";
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reg = <0x34000 0x4000>, <0x100d000 0x1000>;
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interrupts = <130 0x2 0 0>;
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cell-index = <0xd>;
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};
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};
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&soc {
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#address-cells = <1>;
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#size-cells = <1>;
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device_type = "soc";
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compatible = "simple-bus";
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soc-sram-error {
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compatible = "fsl,soc-sram-error";
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interrupts = <16 2 1 2>;
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};
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corenet-law@0 {
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compatible = "fsl,corenet-law";
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reg = <0x0 0x1000>;
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fsl,num-laws = <32>;
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};
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ddr1: memory-controller@8000 {
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compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
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reg = <0x8000 0x1000>;
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interrupts = <16 2 1 8>;
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};
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cpc: l3-cache-controller@10000 {
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compatible = "fsl,b4-l3-cache-controller", "cache";
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reg = <0x10000 0x1000>;
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interrupts = <16 2 1 4>;
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};
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corenet-cf@18000 {
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compatible = "fsl,corenet2-cf", "fsl,corenet-cf";
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reg = <0x18000 0x1000>;
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interrupts = <16 2 1 0>;
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fsl,ccf-num-csdids = <32>;
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fsl,ccf-num-snoopids = <32>;
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};
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iommu@20000 {
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compatible = "fsl,pamu-v1.0", "fsl,pamu";
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reg = <0x20000 0x4000>;
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fsl,portid-mapping = <0x8000>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <
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24 2 0 0
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16 2 1 1>;
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/* PCIe, DMA, SRIO */
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pamu0: pamu@0 {
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reg = <0 0x1000>;
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fsl,primary-cache-geometry = <8 1>;
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fsl,secondary-cache-geometry = <32 2>;
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};
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/* AXI2, Maple */
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pamu1: pamu@1000 {
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reg = <0x1000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <32 2>;
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};
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/* Q/BMan */
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pamu2: pamu@2000 {
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reg = <0x2000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <32 2>;
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};
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/* AXI1, FMAN */
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pamu3: pamu@3000 {
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reg = <0x3000 0x1000>;
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fsl,primary-cache-geometry = <32 1>;
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fsl,secondary-cache-geometry = <32 2>;
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};
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};
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/include/ "qoriq-mpic4.3.dtsi"
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guts: global-utilities@e0000 {
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compatible = "fsl,b4-device-config";
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reg = <0xe0000 0xe00>;
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fsl,has-rstcr;
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fsl,liodn-bits = <12>;
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};
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/include/ "qoriq-clockgen2.dtsi"
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rcpm: global-utilities@e2000 {
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compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
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reg = <0xe2000 0x1000>;
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};
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/include/ "elo3-dma-0.dtsi"
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dma@100300 {
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fsl,iommu-parent = <&pamu0>;
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fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
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};
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/include/ "elo3-dma-1.dtsi"
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dma@101300 {
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fsl,iommu-parent = <&pamu0>;
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fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
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};
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/include/ "qonverge-usb2-dr-0.dtsi"
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usb0: usb@210000 {
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compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
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fsl,iommu-parent = <&pamu1>;
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fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
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};
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/include/ "qoriq-espi-0.dtsi"
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spi@110000 {
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fsl,espi-num-chipselects = <4>;
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};
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/include/ "qoriq-esdhc-0.dtsi"
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sdhc@114000 {
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sdhci,auto-cmd12;
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fsl,iommu-parent = <&pamu1>;
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fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
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};
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/include/ "qoriq-i2c-0.dtsi"
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/include/ "qoriq-i2c-1.dtsi"
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/include/ "qoriq-duart-0.dtsi"
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/include/ "qoriq-duart-1.dtsi"
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/include/ "qoriq-sec5.3-0.dtsi"
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/include/ "qoriq-qman3.dtsi"
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qman: qman@318000 {
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interrupts = <16 2 1 28>;
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};
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/include/ "qoriq-bman1.dtsi"
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bman: bman@31a000 {
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interrupts = <16 2 1 29>;
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};
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/include/ "qoriq-fman3-0.dtsi"
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/include/ "qoriq-fman3-0-1g-0.dtsi"
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/include/ "qoriq-fman3-0-1g-1.dtsi"
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/include/ "qoriq-fman3-0-1g-2.dtsi"
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/include/ "qoriq-fman3-0-1g-3.dtsi"
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fman@400000 {
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interrupts = <96 2 0 0>, <16 2 1 30>;
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muram@0 {
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compatible = "fsl,fman-muram";
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reg = <0x0 0x80000>;
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};
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enet0: ethernet@e0000 {
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};
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enet1: ethernet@e2000 {
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};
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enet2: ethernet@e4000 {
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};
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enet3: ethernet@e6000 {
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};
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mdio@fc000 {
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interrupts = <100 1 0 0>;
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};
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mdio@fd000 {
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interrupts = <101 1 0 0>;
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};
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};
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};
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