/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
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*/
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#ifndef __ASM_SN_INTR_H
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#define __ASM_SN_INTR_H
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/*
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* Macros to manipulate the interrupt register on the calling hub chip.
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*/
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#define LOCAL_HUB_SEND_INTR(level) \
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LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
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#define REMOTE_HUB_SEND_INTR(hub, level) \
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REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
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/*
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* When clearing the interrupt, make sure this clear does make it
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* to the hub. Otherwise we could end up losing interrupts.
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* We do an uncached load of the int_pend0 register to ensure this.
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*/
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#define LOCAL_HUB_CLR_INTR(level) \
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do { \
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LOCAL_HUB_S(PI_INT_PEND_MOD, (level)); \
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LOCAL_HUB_L(PI_INT_PEND0); \
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} while (0);
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#define REMOTE_HUB_CLR_INTR(hub, level) \
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do { \
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nasid_t __hub = (hub); \
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\
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REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level)); \
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REMOTE_HUB_L(__hub, PI_INT_PEND0); \
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} while (0);
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/*
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* Hard-coded interrupt levels:
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*/
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/*
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* L0 = SW1
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* L1 = SW2
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* L2 = INT_PEND0
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* L3 = INT_PEND1
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* L4 = RTC
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* L5 = Profiling Timer
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* L6 = Hub Errors
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* L7 = Count/Compare (T5 counters)
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*/
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/*
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* INT_PEND0 hard-coded bits.
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*/
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/*
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* INT_PEND0 bits determined by hardware:
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*/
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#define RESERVED_INTR 0 /* What is this bit? */
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#define GFX_INTR_A 1
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#define GFX_INTR_B 2
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#define PG_MIG_INTR 3
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#define UART_INTR 4
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#define CC_PEND_A 5
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#define CC_PEND_B 6
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/*
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* INT_PEND0 used by the kernel for itself ...
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*/
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#define CPU_RESCHED_A_IRQ 7
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#define CPU_RESCHED_B_IRQ 8
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#define CPU_CALL_A_IRQ 9
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#define CPU_CALL_B_IRQ 10
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/*
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* INT_PEND1 hard-coded bits:
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*/
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#define NI_BRDCAST_ERR_A 39
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#define NI_BRDCAST_ERR_B 40
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#define LLP_PFAIL_INTR_A 41 /* see ml/SN/SN0/sysctlr.c */
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#define LLP_PFAIL_INTR_B 42
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#define TLB_INTR_A 43 /* used for tlb flush random */
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#define TLB_INTR_B 44
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#define IP27_INTR_0 45 /* Reserved for PROM use */
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#define IP27_INTR_1 46 /* do not use in Kernel */
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#define IP27_INTR_2 47
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#define IP27_INTR_3 48
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#define IP27_INTR_4 49
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#define IP27_INTR_5 50
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#define IP27_INTR_6 51
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#define IP27_INTR_7 52
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#define BRIDGE_ERROR_INTR 53 /* Setup by PROM to catch */
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/* Bridge Errors */
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#define DEBUG_INTR_A 54
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#define DEBUG_INTR_B 55 /* Used by symmon to stop all cpus */
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#define IO_ERROR_INTR 57 /* Setup by PROM */
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#define CLK_ERR_INTR 58
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#define COR_ERR_INTR_A 59
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#define COR_ERR_INTR_B 60
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#define MD_COR_ERR_INTR 61
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#define NI_ERROR_INTR 62
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#define MSC_PANIC_INTR 63
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#endif /* __ASM_SN_INTR_H */
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