/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* IDT RC32434 specific CPU feature overrides
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*
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* Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
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*
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* This file was derived from: include/asm-mips/cpu-features.h
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* Copyright (C) 2003, 2004 Ralf Baechle
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* Copyright (C) 2004 Maciej W. Rozycki
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*/
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#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
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#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
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/*
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* The IDT RC32434 SOC has a built-in MIPS 4Kc core.
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*/
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#define cpu_has_tlb 1
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#define cpu_has_4kex 1
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#define cpu_has_3k_cache 0
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#define cpu_has_4k_cache 1
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#define cpu_has_tx39_cache 0
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#define cpu_has_sb1_cache 0
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#define cpu_has_fpu 0
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#define cpu_has_32fpr 0
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#define cpu_has_counter 1
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#define cpu_has_watch 1
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#define cpu_has_divec 1
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#define cpu_has_vce 0
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#define cpu_has_cache_cdex_p 0
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#define cpu_has_cache_cdex_s 0
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#define cpu_has_prefetch 1
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#define cpu_has_mcheck 1
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#define cpu_has_ejtag 1
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#define cpu_has_llsc 1
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#define cpu_has_mips16 0
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#define cpu_has_mips16e2 0
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#define cpu_has_mdmx 0
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#define cpu_has_mips3d 0
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#define cpu_has_smartmips 0
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#define cpu_has_vtag_icache 0
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#define cpu_has_mips32r1 1
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#define cpu_has_mips32r2 0
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 0
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#define cpu_has_dsp 0
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#define cpu_has_dsp2 0
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#define cpu_has_mipsmt 0
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/* #define cpu_has_nofpuex ? */
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#define cpu_has_64bits 0
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#define cpu_has_64bit_zero_reg 0
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#define cpu_has_64bit_gp_regs 0
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#define cpu_has_inclusive_pcaches 0
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#define cpu_dcache_line_size() 16
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#define cpu_icache_line_size() 16
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#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
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