/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Generic support for queying CPU info
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*
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* Copyright (C) 2007-2009 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2007-2009 PetaLogix
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* Copyright (C) 2007 John Williams <jwilliams@itee.uq.edu.au>
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*/
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#ifndef _ASM_MICROBLAZE_CPUINFO_H
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#define _ASM_MICROBLAZE_CPUINFO_H
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#include <linux/of.h>
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/* CPU Version and FPGA Family code conversion table type */
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struct cpu_ver_key {
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const char *s;
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const unsigned k;
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};
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extern const struct cpu_ver_key cpu_ver_lookup[];
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struct family_string_key {
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const char *s;
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const unsigned k;
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};
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extern const struct family_string_key family_string_lookup[];
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struct cpuinfo {
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/* Core CPU configuration */
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u32 use_instr;
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u32 use_mult;
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u32 use_fpu;
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u32 use_exc;
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u32 ver_code;
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u32 mmu;
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u32 mmu_privins;
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u32 endian;
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/* CPU caches */
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u32 use_icache;
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u32 icache_tagbits;
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u32 icache_write;
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u32 icache_line_length;
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u32 icache_size;
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unsigned long icache_base;
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unsigned long icache_high;
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u32 use_dcache;
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u32 dcache_tagbits;
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u32 dcache_write;
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u32 dcache_line_length;
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u32 dcache_size;
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u32 dcache_wb;
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unsigned long dcache_base;
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unsigned long dcache_high;
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/* Bus connections */
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u32 use_dopb;
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u32 use_iopb;
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u32 use_dlmb;
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u32 use_ilmb;
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u32 num_fsl;
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/* CPU interrupt line info */
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u32 irq_edge;
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u32 irq_positive;
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u32 area_optimised;
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/* HW debug support */
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u32 hw_debug;
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u32 num_pc_brk;
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u32 num_rd_brk;
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u32 num_wr_brk;
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u32 cpu_clock_freq; /* store real freq of cpu */
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/* FPGA family */
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u32 fpga_family_code;
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/* User define */
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u32 pvr_user1;
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u32 pvr_user2;
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};
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extern struct cpuinfo cpuinfo;
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/* fwd declarations of the various CPUinfo populators */
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void setup_cpuinfo(void);
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void setup_cpuinfo_clk(void);
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void set_cpuinfo_static(struct cpuinfo *ci, struct device_node *cpu);
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void set_cpuinfo_pvr_full(struct cpuinfo *ci, struct device_node *cpu);
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static inline unsigned int fcpu(struct device_node *cpu, char *n)
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{
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u32 val = 0;
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of_property_read_u32(cpu, n, &val);
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return val;
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}
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#endif /* _ASM_MICROBLAZE_CPUINFO_H */
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