/*
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* fp_decode.h
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*
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* Copyright Roman Zippel, 1997. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, and the entire permission notice in its entirety,
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* including the disclaimer of warranties.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote
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* products derived from this software without specific prior
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* written permission.
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*
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* ALTERNATIVELY, this product may be distributed under the terms of
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* the GNU General Public License, in which case the provisions of the GPL are
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* required INSTEAD OF the above restrictions. (This clause is
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* necessary due to a potential bad interaction between the GPL and
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* the restrictions contained in a BSD-style copyright.)
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _FP_DECODE_H
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#define _FP_DECODE_H
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/* These macros do the dirty work of the instr decoding, several variables
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* can be defined in the source file to modify the work of these macros,
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* currently the following variables are used:
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* ...
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* The register usage:
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* d0 - will contain source operand for data direct mode,
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* otherwise scratch register
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* d1 - upper 16bit are reserved for caller
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* lower 16bit may contain further arguments,
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* is destroyed during decoding
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* d2 - contains first two instruction words,
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* first word will be used for extension word
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* a0 - will point to source/dest operand for any indirect mode
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* otherwise scratch register
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* a1 - scratch register
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* a2 - base addr to the task structure
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*
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* the current implementation doesn't check for every disallowed
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* addressing mode (e.g. pc relative modes as destination), as long
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* as it only means a new addressing mode, which should not appear
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* in a program and that doesn't crash the emulation, I think it's
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* not a problem to allow these modes.
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*/
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do_fmovem=0
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do_fmovem_cr=0
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do_no_pc_mode=0
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do_fscc=0
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| first decoding of the instr type
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| this separates the conditional instr
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.macro fp_decode_cond_instr_type
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bfextu %d2{#8,#2},%d0
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jmp ([0f:w,%pc,%d0*4])
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.align 4
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0:
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| .long "f<op>","fscc/fdbcc"
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| .long "fbccw","fbccl"
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.endm
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| second decoding of the instr type
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| this separates most move instr
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.macro fp_decode_move_instr_type
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bfextu %d2{#16,#3},%d0
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jmp ([0f:w,%pc,%d0*4])
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.align 4
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0:
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| .long "f<op> fpx,fpx","invalid instr"
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| .long "f<op> <ea>,fpx","fmove fpx,<ea>"
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| .long "fmovem <ea>,fpcr","fmovem <ea>,fpx"
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| .long "fmovem fpcr,<ea>","fmovem fpx,<ea>"
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.endm
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| extract the source specifier, specifies
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| either source fp register or data format
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.macro fp_decode_sourcespec
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bfextu %d2{#19,#3},%d0
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.endm
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| decode destination format for fmove reg,ea
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.macro fp_decode_dest_format
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bfextu %d2{#19,#3},%d0
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.endm
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| decode source register for fmove reg,ea
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.macro fp_decode_src_reg
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bfextu %d2{#22,#3},%d0
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.endm
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| extract the addressing mode
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| it depends on the instr which of the modes is valid
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.macro fp_decode_addr_mode
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bfextu %d2{#10,#3},%d0
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jmp ([0f:w,%pc,%d0*4])
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.align 4
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0:
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| .long "data register direct","addr register direct"
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| .long "addr register indirect"
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| .long "addr register indirect postincrement"
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| .long "addr register indirect predecrement"
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| .long "addr register + index16"
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| .long "extension mode1","extension mode2"
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.endm
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| extract the register for the addressing mode
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.macro fp_decode_addr_reg
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bfextu %d2{#13,#3},%d0
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.endm
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| decode the 8bit displacement from the brief extension word
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.macro fp_decode_disp8
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move.b %d2,%d0
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ext.w %d0
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.endm
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| decode the index of the brief/full extension word
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.macro fp_decode_index
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bfextu %d2{#17,#3},%d0 | get the register nr
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btst #15,%d2 | test for data/addr register
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jne 1\@f
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printf PDECODE,"d%d",1,%d0
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jsr fp_get_data_reg
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jra 2\@f
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1\@: printf PDECODE,"a%d",1,%d0
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jsr fp_get_addr_reg
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move.l %a0,%d0
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2\@:
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debug lea "'l'.w,%a0"
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btst #11,%d2 | 16/32 bit size?
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jne 3\@f
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debug lea "'w'.w,%a0"
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ext.l %d0
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3\@: printf PDECODE,":%c",1,%a0
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move.w %d2,%d1 | scale factor
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rol.w #7,%d1
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and.w #3,%d1
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debug move.l "%d1,-(%sp)"
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debug ext.l "%d1"
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printf PDECODE,":%d",1,%d1
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debug move.l "(%sp)+,%d1"
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lsl.l %d1,%d0
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.endm
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| decode the base displacement size
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.macro fp_decode_basedisp
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bfextu %d2{#26,#2},%d0
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jmp ([0f:w,%pc,%d0*4])
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.align 4
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0:
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| .long "reserved","null displacement"
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| .long "word displacement","long displacement"
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.endm
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.macro fp_decode_outerdisp
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bfextu %d2{#30,#2},%d0
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jmp ([0f:w,%pc,%d0*4])
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.align 4
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0:
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| .long "no memory indirect action/reserved","null outer displacement"
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| .long "word outer displacement","long outer displacement"
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.endm
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| get the extension word and test for brief or full extension type
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.macro fp_get_test_extword label
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fp_get_instr_word %d2,fp_err_ua1
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btst #8,%d2
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jne \label
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.endm
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| test if %pc is the base register for the indirect addr mode
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.macro fp_test_basereg_d16 label
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btst #20,%d2
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jeq \label
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.endm
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| test if %pc is the base register for one of the extended modes
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.macro fp_test_basereg_ext label
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btst #19,%d2
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jeq \label
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.endm
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.macro fp_test_suppr_index label
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btst #6,%d2
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jne \label
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.endm
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| addressing mode: data register direct
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.macro fp_mode_data_direct
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fp_decode_addr_reg
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printf PDECODE,"d%d",1,%d0
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.endm
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| addressing mode: address register indirect
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.macro fp_mode_addr_indirect
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fp_decode_addr_reg
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printf PDECODE,"(a%d)",1,%d0
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jsr fp_get_addr_reg
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.endm
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| adjust stack for byte moves from/to stack
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.macro fp_test_sp_byte_move
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.if !do_fmovem
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.if do_fscc
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move.w #6,%d1
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.endif
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cmp.w #7,%d0
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jne 1\@f
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.if !do_fscc
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cmp.w #6,%d1
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jne 1\@f
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.endif
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move.w #4,%d1
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1\@:
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.endif
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.endm
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| addressing mode: address register indirect with postincrement
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.macro fp_mode_addr_indirect_postinc
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fp_decode_addr_reg
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printf PDECODE,"(a%d)+",1,%d0
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fp_test_sp_byte_move
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jsr fp_get_addr_reg
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move.l %a0,%a1 | save addr
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.if do_fmovem
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lea (%a0,%d1.w*4),%a0
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.if !do_fmovem_cr
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lea (%a0,%d1.w*8),%a0
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.endif
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.else
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add.w (fp_datasize,%d1.w*2),%a0
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.endif
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jsr fp_put_addr_reg
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move.l %a1,%a0
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.endm
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| addressing mode: address register indirect with predecrement
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.macro fp_mode_addr_indirect_predec
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fp_decode_addr_reg
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printf PDECODE,"-(a%d)",1,%d0
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fp_test_sp_byte_move
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jsr fp_get_addr_reg
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.if do_fmovem
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.if !do_fmovem_cr
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lea (-12,%a0),%a1 | setup to addr of 1st reg to move
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neg.w %d1
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lea (%a0,%d1.w*4),%a0
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add.w %d1,%d1
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lea (%a0,%d1.w*4),%a0
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jsr fp_put_addr_reg
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move.l %a1,%a0
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.else
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neg.w %d1
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lea (%a0,%d1.w*4),%a0
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jsr fp_put_addr_reg
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.endif
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.else
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sub.w (fp_datasize,%d1.w*2),%a0
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jsr fp_put_addr_reg
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.endif
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.endm
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| addressing mode: address register/programm counter indirect
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| with 16bit displacement
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.macro fp_mode_addr_indirect_disp16
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.if !do_no_pc_mode
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fp_test_basereg_d16 1f
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printf PDECODE,"pc"
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fp_get_pc %a0
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jra 2f
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.endif
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1: fp_decode_addr_reg
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printf PDECODE,"a%d",1,%d0
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jsr fp_get_addr_reg
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2: fp_get_instr_word %a1,fp_err_ua1
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printf PDECODE,"@(%x)",1,%a1
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add.l %a1,%a0
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.endm
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| perform preindex (if I/IS == 0xx and xx != 00)
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.macro fp_do_preindex
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moveq #3,%d0
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and.w %d2,%d0
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jeq 1f
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btst #2,%d2
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jne 1f
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printf PDECODE,")@("
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getuser.l (%a1),%a1,fp_err_ua1,%a1
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debug jra "2f"
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1: printf PDECODE,","
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2:
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.endm
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| perform postindex (if I/IS == 1xx)
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.macro fp_do_postindex
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btst #2,%d2
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jeq 1f
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printf PDECODE,")@("
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getuser.l (%a1),%a1,fp_err_ua1,%a1
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debug jra "2f"
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1: printf PDECODE,","
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2:
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.endm
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| all other indirect addressing modes will finally end up here
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.macro fp_mode_addr_indirect_extmode0
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.if !do_no_pc_mode
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fp_test_basereg_ext 1f
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printf PDECODE,"pc"
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fp_get_pc %a0
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jra 2f
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.endif
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1: fp_decode_addr_reg
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printf PDECODE,"a%d",1,%d0
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jsr fp_get_addr_reg
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2: move.l %a0,%a1
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swap %d2
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fp_get_test_extword 3f
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| addressing mode: address register/programm counter indirect
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| with index and 8bit displacement
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fp_decode_disp8
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debug ext.l "%d0"
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printf PDECODE,"@(%x,",1,%d0
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add.w %d0,%a1
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fp_decode_index
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add.l %d0,%a1
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printf PDECODE,")"
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jra 9f
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3: | addressing mode: address register/programm counter memory indirect
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| with base and/or outer displacement
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btst #7,%d2 | base register suppressed?
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jeq 1f
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printf PDECODE,"!"
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sub.l %a1,%a1
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1: printf PDECODE,"@("
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fp_decode_basedisp
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.long fp_ill,1f
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.long 2f,3f
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#ifdef FPU_EMU_DEBUG
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1: printf PDECODE,"0" | null base displacement
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jra 1f
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#endif
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2: fp_get_instr_word %a0,fp_err_ua1 | 16bit base displacement
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printf PDECODE,"%x:w",1,%a0
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jra 4f
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3: fp_get_instr_long %a0,fp_err_ua1 | 32bit base displacement
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printf PDECODE,"%x:l",1,%a0
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4: add.l %a0,%a1
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1:
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fp_do_postindex
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fp_test_suppr_index 1f
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fp_decode_index
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add.l %d0,%a1
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1: fp_do_preindex
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fp_decode_outerdisp
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.long 5f,1f
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.long 2f,3f
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#ifdef FPU_EMU_DEBUG
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1: printf PDECODE,"0" | null outer displacement
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jra 1f
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#endif
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2: fp_get_instr_word %a0,fp_err_ua1 | 16bit outer displacement
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printf PDECODE,"%x:w",1,%a0
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jra 4f
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3: fp_get_instr_long %a0,fp_err_ua1 | 32bit outer displacement
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printf PDECODE,"%x:l",1,%a0
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4: add.l %a0,%a1
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1:
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5: printf PDECODE,")"
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9: move.l %a1,%a0
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swap %d2
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.endm
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| get the absolute short address from user space
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.macro fp_mode_abs_short
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fp_get_instr_word %a0,fp_err_ua1
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printf PDECODE,"%x.w",1,%a0
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.endm
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| get the absolute long address from user space
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.macro fp_mode_abs_long
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fp_get_instr_long %a0,fp_err_ua1
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printf PDECODE,"%x.l",1,%a0
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.endm
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#endif /* _FP_DECODE_H */
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