/****************************************************************************/
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/*
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* m54xxpci.h -- ColdFire 547x and 548x PCI bus support
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*
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* (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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/****************************************************************************/
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#ifndef M54XXPCI_H
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#define M54XXPCI_H
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/****************************************************************************/
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/*
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* The core set of PCI support registers are mapped into the MBAR region.
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*/
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#define PCIIDR (CONFIG_MBAR + 0xb00) /* PCI device/vendor ID */
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#define PCISCR (CONFIG_MBAR + 0xb04) /* PCI status/command */
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#define PCICCRIR (CONFIG_MBAR + 0xb08) /* PCI class/revision */
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#define PCICR1 (CONFIG_MBAR + 0xb0c) /* PCI configuration 1 */
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#define PCIBAR0 (CONFIG_MBAR + 0xb10) /* PCI base address 0 */
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#define PCIBAR1 (CONFIG_MBAR + 0xb14) /* PCI base address 1 */
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#define PCICCPR (CONFIG_MBAR + 0xb28) /* PCI cardbus CIS pointer */
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#define PCISID (CONFIG_MBAR + 0xb2c) /* PCI subsystem IDs */
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#define PCIERBAR (CONFIG_MBAR + 0xb30) /* PCI expansion ROM */
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#define PCICPR (CONFIG_MBAR + 0xb34) /* PCI capabilities pointer */
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#define PCICR2 (CONFIG_MBAR + 0xb3c) /* PCI configuration 2 */
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#define PCIGSCR (CONFIG_MBAR + 0xb60) /* Global status/control */
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#define PCITBATR0 (CONFIG_MBAR + 0xb64) /* Target base translation 0 */
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#define PCITBATR1 (CONFIG_MBAR + 0xb68) /* Target base translation 1 */
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#define PCITCR (CONFIG_MBAR + 0xb6c) /* Target control */
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#define PCIIW0BTAR (CONFIG_MBAR + 0xb70) /* Initiator window 0 */
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#define PCIIW1BTAR (CONFIG_MBAR + 0xb74) /* Initiator window 1 */
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#define PCIIW2BTAR (CONFIG_MBAR + 0xb78) /* Initiator window 2 */
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#define PCIIWCR (CONFIG_MBAR + 0xb80) /* Initiator window config */
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#define PCIICR (CONFIG_MBAR + 0xb84) /* Initiator control */
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#define PCIISR (CONFIG_MBAR + 0xb88) /* Initiator status */
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#define PCICAR (CONFIG_MBAR + 0xbf8) /* Configuration address */
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#define PCITPSR (CONFIG_MBAR + 0x8400) /* TX packet size */
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#define PCITSAR (CONFIG_MBAR + 0x8404) /* TX start address */
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#define PCITTCR (CONFIG_MBAR + 0x8408) /* TX transaction control */
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#define PCITER (CONFIG_MBAR + 0x840c) /* TX enables */
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#define PCITNAR (CONFIG_MBAR + 0x8410) /* TX next address */
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#define PCITLWR (CONFIG_MBAR + 0x8414) /* TX last word */
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#define PCITDCR (CONFIG_MBAR + 0x8418) /* TX done counts */
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#define PCITSR (CONFIG_MBAR + 0x841c) /* TX status */
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#define PCITFDR (CONFIG_MBAR + 0x8440) /* TX FIFO data */
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#define PCITFSR (CONFIG_MBAR + 0x8444) /* TX FIFO status */
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#define PCITFCR (CONFIG_MBAR + 0x8448) /* TX FIFO control */
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#define PCITFAR (CONFIG_MBAR + 0x844c) /* TX FIFO alarm */
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#define PCITFRPR (CONFIG_MBAR + 0x8450) /* TX FIFO read pointer */
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#define PCITFWPR (CONFIG_MBAR + 0x8454) /* TX FIFO write pointer */
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#define PCIRPSR (CONFIG_MBAR + 0x8480) /* RX packet size */
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#define PCIRSAR (CONFIG_MBAR + 0x8484) /* RX start address */
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#define PCIRTCR (CONFIG_MBAR + 0x8488) /* RX transaction control */
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#define PCIRER (CONFIG_MBAR + 0x848c) /* RX enables */
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#define PCIRNAR (CONFIG_MBAR + 0x8490) /* RX next address */
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#define PCIRDCR (CONFIG_MBAR + 0x8498) /* RX done counts */
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#define PCIRSR (CONFIG_MBAR + 0x849c) /* RX status */
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#define PCIRFDR (CONFIG_MBAR + 0x84c0) /* RX FIFO data */
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#define PCIRFSR (CONFIG_MBAR + 0x84c4) /* RX FIFO status */
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#define PCIRFCR (CONFIG_MBAR + 0x84c8) /* RX FIFO control */
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#define PCIRFAR (CONFIG_MBAR + 0x84cc) /* RX FIFO alarm */
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#define PCIRFRPR (CONFIG_MBAR + 0x84d0) /* RX FIFO read pointer */
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#define PCIRFWPR (CONFIG_MBAR + 0x84d4) /* RX FIFO write pointer */
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#define PACR (CONFIG_MBAR + 0xc00) /* PCI arbiter control */
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#define PASR (CONFIG_MBAR + 0xc04) /* PCI arbiter status */
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/*
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* Definitions for the Global status and control register.
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*/
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#define PCIGSCR_PE 0x20000000 /* Parity error detected */
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#define PCIGSCR_SE 0x10000000 /* System error detected */
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#define PCIGSCR_XCLKBIN 0x07000000 /* XLB2CLKIN mask */
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#define PCIGSCR_PEE 0x00002000 /* Parity error intr enable */
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#define PCIGSCR_SEE 0x00001000 /* System error intr enable */
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#define PCIGSCR_RESET 0x00000001 /* Reset bit */
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/*
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* Bit definitions for the PCICAR configuration address register.
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*/
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#define PCICAR_E 0x80000000 /* Enable config space */
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#define PCICAR_BUSN 16 /* Move bus bits */
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#define PCICAR_DEVFNN 8 /* Move devfn bits */
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#define PCICAR_DWORDN 0 /* Move dword bits */
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/*
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* The initiator windows hold the memory and IO mapping information.
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* This macro creates the register values from the desired addresses.
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*/
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#define WXBTAR(hostaddr, pciaddr, size) \
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(((hostaddr) & 0xff000000) | \
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((((size) - 1) & 0xff000000) >> 8) | \
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(((pciaddr) & 0xff000000) >> 16))
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#define PCIIWCR_W0_MEM 0x00000000 /* Window 0 is memory */
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#define PCIIWCR_W0_IO 0x08000000 /* Window 0 is IO */
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#define PCIIWCR_W0_MRD 0x00000000 /* Window 0 memory read */
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#define PCIIWCR_W0_MRDL 0x02000000 /* Window 0 memory read line */
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#define PCIIWCR_W0_MRDM 0x04000000 /* Window 0 memory read mult */
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#define PCIIWCR_W0_E 0x01000000 /* Window 0 enable */
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#define PCIIWCR_W1_MEM 0x00000000 /* Window 0 is memory */
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#define PCIIWCR_W1_IO 0x00080000 /* Window 0 is IO */
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#define PCIIWCR_W1_MRD 0x00000000 /* Window 0 memory read */
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#define PCIIWCR_W1_MRDL 0x00020000 /* Window 0 memory read line */
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#define PCIIWCR_W1_MRDM 0x00040000 /* Window 0 memory read mult */
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#define PCIIWCR_W1_E 0x00010000 /* Window 0 enable */
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/*
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* Bit definitions for the PCIBATR registers.
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*/
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#define PCITBATR0_E 0x00000001 /* Enable window 0 */
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#define PCITBATR1_E 0x00000001 /* Enable window 1 */
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/*
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* PCI arbiter support definitions and macros.
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*/
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#define PACR_INTMPRI 0x00000001
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#define PACR_EXTMPRI(x) (((x) & 0x1f) << 1)
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#define PACR_INTMINTE 0x00010000
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#define PACR_EXTMINTE(x) (((x) & 0x1f) << 17)
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#define PACR_PKMD 0x40000000
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#define PACR_DS 0x80000000
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#define PCICR1_CL(x) ((x) & 0xf) /* Cacheline size field */
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#define PCICR1_LT(x) (((x) & 0xff) << 8) /* Latency timer field */
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/****************************************************************************/
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#endif /* M54XXPCI_H */
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