/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* m5441xsim.h -- Coldfire 5441x register definitions
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*
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* (C) Copyright 2012, Steven King <sfking@fdwdc.com>
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*/
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#ifndef m5441xsim_h
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#define m5441xsim_h
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#define CPU_NAME "COLDFIRE(m5441x)"
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#define CPU_INSTR_PER_JIFFY 2
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#define MCF_BUSCLK (MCF_CLK / 2)
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#define MACHINE MACH_M5441X
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#define FPUTYPE 0
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#define IOMEMBASE 0xe0000000
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#define IOMEMSIZE 0x20000000
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#include <asm/m54xxacr.h>
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/*
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* Reset Controller Module.
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*/
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#define MCF_RCR 0xec090000
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#define MCF_RSR 0xec090001
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#define MCF_RCR_SWRESET 0x80 /* Software reset bit */
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#define MCF_RCR_FRCSTOUT 0x40 /* Force external reset */
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/*
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* Interrupt Controller Modules.
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*/
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/* the 5441x have 3 interrupt controllers, each control 64 interrupts */
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#define MCFINT_VECBASE 64
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#define MCFINT0_VECBASE MCFINT_VECBASE
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#define MCFINT1_VECBASE (MCFINT0_VECBASE + 64)
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#define MCFINT2_VECBASE (MCFINT1_VECBASE + 64)
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/* interrupt controller 0 */
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#define MCFINTC0_SIMR 0xfc04801c
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#define MCFINTC0_CIMR 0xfc04801d
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#define MCFINTC0_ICR0 0xfc048040
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/* interrupt controller 1 */
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#define MCFINTC1_SIMR 0xfc04c01c
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#define MCFINTC1_CIMR 0xfc04c01d
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#define MCFINTC1_ICR0 0xfc04c040
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/* interrupt controller 2 */
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#define MCFINTC2_SIMR 0xfc05001c
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#define MCFINTC2_CIMR 0xfc05001d
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#define MCFINTC2_ICR0 0xfc050040
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/* on interrupt controller 0 */
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#define MCFINT0_EPORT0 1
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#define MCFINT0_UART0 26
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#define MCFINT0_UART1 27
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#define MCFINT0_UART2 28
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#define MCFINT0_UART3 29
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#define MCFINT0_I2C0 30
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#define MCFINT0_DSPI0 31
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#define MCFINT0_TIMER0 32
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#define MCFINT0_TIMER1 33
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#define MCFINT0_TIMER2 34
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#define MCFINT0_TIMER3 35
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#define MCFINT0_FECRX0 36
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#define MCFINT0_FECTX0 40
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#define MCFINT0_FECENTC0 42
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#define MCFINT0_FECRX1 49
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#define MCFINT0_FECTX1 53
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#define MCFINT0_FECENTC1 55
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/* on interrupt controller 1 */
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#define MCFINT1_UART4 48
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#define MCFINT1_UART5 49
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#define MCFINT1_UART6 50
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#define MCFINT1_UART7 51
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#define MCFINT1_UART8 52
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#define MCFINT1_UART9 53
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#define MCFINT1_DSPI1 54
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#define MCFINT1_DSPI2 55
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#define MCFINT1_DSPI3 56
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#define MCFINT1_I2C1 57
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#define MCFINT1_I2C2 58
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#define MCFINT1_I2C3 59
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#define MCFINT1_I2C4 60
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#define MCFINT1_I2C5 61
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/* on interrupt controller 2 */
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#define MCFINT2_PIT0 13
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#define MCFINT2_PIT1 14
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#define MCFINT2_PIT2 15
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#define MCFINT2_PIT3 16
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#define MCFINT2_RTC 26
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/*
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* PIT timer module.
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*/
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#define MCFPIT_BASE0 0xFC080000 /* Base address of TIMER0 */
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#define MCFPIT_BASE1 0xFC084000 /* Base address of TIMER1 */
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#define MCFPIT_BASE2 0xFC088000 /* Base address of TIMER2 */
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#define MCFPIT_BASE3 0xFC08C000 /* Base address of TIMER3 */
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#define MCF_IRQ_PIT1 (MCFINT2_VECBASE + MCFINT2_PIT1)
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/*
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* Power Management
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*/
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#define MCFPM_WCR 0xfc040013
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#define MCFPM_PPMSR0 0xfc04002c
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#define MCFPM_PPMCR0 0xfc04002d
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#define MCFPM_PPMSR1 0xfc04002e
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#define MCFPM_PPMCR1 0xfc04002f
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#define MCFPM_PPMHR0 0xfc040030
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#define MCFPM_PPMLR0 0xfc040034
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#define MCFPM_PPMHR1 0xfc040038
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#define MCFPM_PPMLR1 0xfc04003c
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#define MCFPM_LPCR 0xec090007
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/*
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* UART module.
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*/
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#define MCFUART_BASE0 0xfc060000 /* Base address of UART0 */
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#define MCFUART_BASE1 0xfc064000 /* Base address of UART1 */
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#define MCFUART_BASE2 0xfc068000 /* Base address of UART2 */
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#define MCFUART_BASE3 0xfc06c000 /* Base address of UART3 */
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#define MCFUART_BASE4 0xec060000 /* Base address of UART4 */
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#define MCFUART_BASE5 0xec064000 /* Base address of UART5 */
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#define MCFUART_BASE6 0xec068000 /* Base address of UART6 */
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#define MCFUART_BASE7 0xec06c000 /* Base address of UART7 */
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#define MCFUART_BASE8 0xec070000 /* Base address of UART8 */
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#define MCFUART_BASE9 0xec074000 /* Base address of UART9 */
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#define MCF_IRQ_UART0 (MCFINT0_VECBASE + MCFINT0_UART0)
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#define MCF_IRQ_UART1 (MCFINT0_VECBASE + MCFINT0_UART1)
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#define MCF_IRQ_UART2 (MCFINT0_VECBASE + MCFINT0_UART2)
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#define MCF_IRQ_UART3 (MCFINT0_VECBASE + MCFINT0_UART3)
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#define MCF_IRQ_UART4 (MCFINT1_VECBASE + MCFINT1_UART4)
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#define MCF_IRQ_UART5 (MCFINT1_VECBASE + MCFINT1_UART5)
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#define MCF_IRQ_UART6 (MCFINT1_VECBASE + MCFINT1_UART6)
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#define MCF_IRQ_UART7 (MCFINT1_VECBASE + MCFINT1_UART7)
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#define MCF_IRQ_UART8 (MCFINT1_VECBASE + MCFINT1_UART8)
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#define MCF_IRQ_UART9 (MCFINT1_VECBASE + MCFINT1_UART9)
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/*
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* FEC modules.
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*/
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#define MCFFEC_BASE0 0xfc0d4000
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#define MCFFEC_SIZE0 0x800
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#define MCF_IRQ_FECRX0 (MCFINT0_VECBASE + MCFINT0_FECRX0)
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#define MCF_IRQ_FECTX0 (MCFINT0_VECBASE + MCFINT0_FECTX0)
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#define MCF_IRQ_FECENTC0 (MCFINT0_VECBASE + MCFINT0_FECENTC0)
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#define MCFFEC_BASE1 0xfc0d8000
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#define MCFFEC_SIZE1 0x800
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#define MCF_IRQ_FECRX1 (MCFINT0_VECBASE + MCFINT0_FECRX1)
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#define MCF_IRQ_FECTX1 (MCFINT0_VECBASE + MCFINT0_FECTX1)
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#define MCF_IRQ_FECENTC1 (MCFINT0_VECBASE + MCFINT0_FECENTC1)
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/*
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* I2C modules.
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*/
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#define MCFI2C_BASE0 0xfc058000
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#define MCFI2C_SIZE0 0x20
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#define MCFI2C_BASE1 0xfc038000
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#define MCFI2C_SIZE1 0x20
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#define MCFI2C_BASE2 0xec010000
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#define MCFI2C_SIZE2 0x20
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#define MCFI2C_BASE3 0xec014000
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#define MCFI2C_SIZE3 0x20
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#define MCFI2C_BASE4 0xec018000
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#define MCFI2C_SIZE4 0x20
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#define MCFI2C_BASE5 0xec01c000
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#define MCFI2C_SIZE5 0x20
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#define MCF_IRQ_I2C0 (MCFINT0_VECBASE + MCFINT0_I2C0)
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#define MCF_IRQ_I2C1 (MCFINT1_VECBASE + MCFINT1_I2C1)
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#define MCF_IRQ_I2C2 (MCFINT1_VECBASE + MCFINT1_I2C2)
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#define MCF_IRQ_I2C3 (MCFINT1_VECBASE + MCFINT1_I2C3)
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#define MCF_IRQ_I2C4 (MCFINT1_VECBASE + MCFINT1_I2C4)
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#define MCF_IRQ_I2C5 (MCFINT1_VECBASE + MCFINT1_I2C5)
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/*
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* EPORT Module.
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*/
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#define MCFEPORT_EPPAR 0xfc090000
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#define MCFEPORT_EPIER 0xfc090003
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#define MCFEPORT_EPFR 0xfc090006
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/*
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* RTC Module.
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*/
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#define MCFRTC_BASE 0xfc0a8000
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#define MCFRTC_SIZE (0xfc0a8840 - 0xfc0a8000)
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#define MCF_IRQ_RTC (MCFINT2_VECBASE + MCFINT2_RTC)
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/*
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* GPIO Module.
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*/
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#define MCFGPIO_PODR_A 0xec094000
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#define MCFGPIO_PODR_B 0xec094001
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#define MCFGPIO_PODR_C 0xec094002
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#define MCFGPIO_PODR_D 0xec094003
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#define MCFGPIO_PODR_E 0xec094004
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#define MCFGPIO_PODR_F 0xec094005
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#define MCFGPIO_PODR_G 0xec094006
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#define MCFGPIO_PODR_H 0xec094007
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#define MCFGPIO_PODR_I 0xec094008
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#define MCFGPIO_PODR_J 0xec094009
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#define MCFGPIO_PODR_K 0xec09400a
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#define MCFGPIO_PDDR_A 0xec09400c
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#define MCFGPIO_PDDR_B 0xec09400d
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#define MCFGPIO_PDDR_C 0xec09400e
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#define MCFGPIO_PDDR_D 0xec09400f
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#define MCFGPIO_PDDR_E 0xec094010
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#define MCFGPIO_PDDR_F 0xec094011
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#define MCFGPIO_PDDR_G 0xec094012
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#define MCFGPIO_PDDR_H 0xec094013
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#define MCFGPIO_PDDR_I 0xec094014
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#define MCFGPIO_PDDR_J 0xec094015
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#define MCFGPIO_PDDR_K 0xec094016
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#define MCFGPIO_PPDSDR_A 0xec094018
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#define MCFGPIO_PPDSDR_B 0xec094019
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#define MCFGPIO_PPDSDR_C 0xec09401a
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#define MCFGPIO_PPDSDR_D 0xec09401b
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#define MCFGPIO_PPDSDR_E 0xec09401c
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#define MCFGPIO_PPDSDR_F 0xec09401d
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#define MCFGPIO_PPDSDR_G 0xec09401e
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#define MCFGPIO_PPDSDR_H 0xec09401f
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#define MCFGPIO_PPDSDR_I 0xec094020
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#define MCFGPIO_PPDSDR_J 0xec094021
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#define MCFGPIO_PPDSDR_K 0xec094022
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#define MCFGPIO_PCLRR_A 0xec094024
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#define MCFGPIO_PCLRR_B 0xec094025
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#define MCFGPIO_PCLRR_C 0xec094026
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#define MCFGPIO_PCLRR_D 0xec094027
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#define MCFGPIO_PCLRR_E 0xec094028
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#define MCFGPIO_PCLRR_F 0xec094029
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#define MCFGPIO_PCLRR_G 0xec09402a
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#define MCFGPIO_PCLRR_H 0xec09402b
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#define MCFGPIO_PCLRR_I 0xec09402c
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#define MCFGPIO_PCLRR_J 0xec09402d
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#define MCFGPIO_PCLRR_K 0xec09402e
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#define MCFGPIO_PAR_FBCTL 0xec094048
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#define MCFGPIO_PAR_BE 0xec094049
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#define MCFGPIO_PAR_CS 0xec09404a
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#define MCFGPIO_PAR_CANI2C 0xec09404b
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#define MCFGPIO_PAR_IRQ0H 0xec09404c
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#define MCFGPIO_PAR_IRQ0L 0xec09404d
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#define MCFGPIO_PAR_DSPIOWH 0xec09404e
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#define MCFGPIO_PAR_DSPIOWL 0xec09404f
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#define MCFGPIO_PAR_TIMER 0xec094050
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#define MCFGPIO_PAR_UART2 0xec094051
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#define MCFGPIO_PAR_UART1 0xec094052
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#define MCFGPIO_PAR_UART0 0xec094053
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#define MCFGPIO_PAR_SDHCH 0xec094054
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#define MCFGPIO_PAR_SDHCL 0xec094055
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#define MCFGPIO_PAR_SIMP0H 0xec094056
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#define MCFGPIO_PAR_SIMP0L 0xec094057
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#define MCFGPIO_PAR_SSI0H 0xec094058
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#define MCFGPIO_PAR_SSI0L 0xec094059
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#define MCFGPIO_PAR_DEBUGH1 0xec09405a
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#define MCFGPIO_PAR_DEBUGH0 0xec09405b
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#define MCFGPIO_PAR_DEBUGl 0xec09405c
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#define MCFGPIO_PAR_FEC 0xec09405e
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/* generalization for generic gpio support */
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#define MCFGPIO_PODR MCFGPIO_PODR_A
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#define MCFGPIO_PDDR MCFGPIO_PDDR_A
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#define MCFGPIO_PPDR MCFGPIO_PPDSDR_A
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#define MCFGPIO_SETR MCFGPIO_PPDSDR_A
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#define MCFGPIO_CLRR MCFGPIO_PCLRR_A
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#define MCFGPIO_IRQ_MIN 17
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#define MCFGPIO_IRQ_MAX 24
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#define MCFGPIO_IRQ_VECBASE (MCFINT_VECBASE - MCFGPIO_IRQ_MIN)
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#define MCFGPIO_PIN_MAX 87
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/*
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* Phase Locked Loop (PLL)
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*/
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#define MCF_PLL_CR 0xFC0C0000
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#define MCF_PLL_DR 0xFC0C0004
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#define MCF_PLL_SR 0xFC0C0008
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/*
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* DSPI module.
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*/
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#define MCFDSPI_BASE0 0xfc05c000
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#define MCFDSPI_BASE1 0xfC03c000
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#define MCF_IRQ_DSPI0 (MCFINT0_VECBASE + MCFINT0_DSPI0)
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#define MCF_IRQ_DSPI1 (MCFINT1_VECBASE + MCFINT1_DSPI1)
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/*
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* eDMA module.
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*/
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#define MCFEDMA_BASE 0xfc044000
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#define MCFEDMA_SIZE 0x4000
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#define MCFINT0_EDMA_INTR0 8
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#define MCFINT0_EDMA_ERR 24
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#define MCFEDMA_EDMA_INTR16 8
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#define MCFEDMA_EDMA_INTR56 0
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#define MCFEDMA_IRQ_INTR0 (MCFINT0_VECBASE + MCFINT0_EDMA_INTR0)
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#define MCFEDMA_IRQ_INTR16 (MCFINT1_VECBASE + MCFEDMA_EDMA_INTR16)
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#define MCFEDMA_IRQ_INTR56 (MCFINT2_VECBASE + MCFEDMA_EDMA_INTR56)
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#define MCFEDMA_IRQ_ERR (MCFINT0_VECBASE + MCFINT0_EDMA_ERR)
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/*
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* esdhc module.
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*/
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#define MCFSDHC_BASE 0xfc0cc000
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#define MCFSDHC_SIZE 256
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#define MCFINT2_SDHC 31
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#define MCF_IRQ_SDHC (MCFINT2_VECBASE + MCFINT2_SDHC)
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#define MCFSDHC_CLK (MCFSDHC_BASE + 0x2c)
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#endif /* m5441xsim_h */
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