// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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max96756_dphy0_osc: max96712-dphy0-oscillator@0 {
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compatible = "fixed-clock";
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#clock-cells = <1>;
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clock-frequency = <25000000>;
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clock-output-names = "max96756-dphy0-osc";
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};
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max96756_dphy0_vcc1v2: max96756-dphy0-vcc1v2 {
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compatible = "regulator-fixed";
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regulator-name = "max96756_dphy0_vcc1v2";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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startup-delay-us = <850>;
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vin-supply = <&vcc5v0_sys>;
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};
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max96756_dphy0_vcc1v8: max96756-dphy0-vcc1v8 {
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compatible = "regulator-fixed";
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regulator-name = "max96756_dphy0_vcc1v8";
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regulator-boot-on;
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regulator-always-on;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <1800000>;
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startup-delay-us = <200>;
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vin-supply = <&vcc_3v3_s3>;
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};
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};
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/**
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* ============================================================================
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* Info DPHY0
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* ============================================================================
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*/
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&csi2_dphy0_hw {
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status = "okay";
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};
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&csi2_dphy0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_dphy0_in_max96756: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&max96756_dphy0_out>;
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data-lanes = <1 2 3 4>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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csidphy0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&mipi2_csi2_input>;
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};
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};
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};
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};
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&i2c7 {
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status = "okay";
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2c7m3_xfer>;
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max96756: max96756@48 {
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compatible = "maxim,max96756";
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status = "okay";
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reg = <0x48>;
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clock-names = "xvclk";
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clocks = <&max96756_dphy0_osc 0>;
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power-domains = <&power RK3588_PD_VI>;
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rockchip,grf = <&sys_grf>;
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pinctrl-names = "default";
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pinctrl-0 = <&max96756_dphy0_pwdn>, <&max96756_dphy0_errb>, <&max96756_dphy0_lock>;
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pwdn-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
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lock-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_HIGH>;
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vcc1v2-supply = <&max96756_dphy0_vcc1v2>;
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vcc1v8-supply = <&max96756_dphy0_vcc1v8>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "max96756";
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rockchip,camera-module-lens-name = "max96756";
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port {
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max96756_dphy0_out: endpoint {
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remote-endpoint = <&mipi_dphy0_in_max96756>;
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data-lanes = <1 2 3 4>;
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};
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};
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};
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};
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&mipi2_csi2 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi2_csi2_input: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&csidphy0_out>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi2_csi2_output: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&cif_mipi2_in>;
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};
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};
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};
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};
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&rkcif_mipi_lvds2 {
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status = "okay";
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/* parameters for do cif reset detecting:
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* index0: monitor mode,
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0 for idle,
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1 for continue,
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2 for trigger,
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3 for hotplug (for nextchip)
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* index1: the frame id to start timer,
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min is 2
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* index2: frame num of monitoring cycle
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* index3: err time for keep monitoring
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after finding out err (ms)
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* index4: csi2 err reference val for resetting
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*/
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rockchip,cif-monitor = <3 2 1 1000 5>;
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port {
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cif_mipi2_in: endpoint {
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remote-endpoint = <&mipi2_csi2_output>;
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};
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};
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};
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/**
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* =============================================================================
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* Common
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* =============================================================================
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*/
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&rkcif {
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status = "okay";
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rockchip,android-usb-camerahal-enable;
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};
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&rkcif_mmu {
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status = "okay";
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};
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&pinctrl {
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max96756-dphy0 {
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max96756_dphy0_pwdn: max96756-dphy0-pwdn {
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rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_output_low>;
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};
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max96756_dphy0_errb: max96756-dphy0-errb {
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rockchip,pins = <3 RK_PD1 RK_FUNC_GPIO &pcfg_pull_none_smt>;
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};
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max96756_dphy0_lock: max96756-dphy0-lock {
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rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none_smt>;
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};
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};
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};
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