// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
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*
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*/
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/ {
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chosen: chosen {
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bootargs = "earlycon=uart8250,mmio32,0xfe660000 console=ttyFIQ0 root=PARTUUID=614e0000-0000 rw rootwait";
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};
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fiq-debugger {
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compatible = "rockchip,fiq-debugger";
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rockchip,serial-id = <2>;
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rockchip,wake-irq = <0>;
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/* If enable uart uses irq instead of fiq */
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rockchip,irq-mode-enable = <1>;
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rockchip,baudrate = <1500000>; /* Only 115200 and 1500000 */
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interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_LOW>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart2m0_xfer>;
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status = "okay";
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};
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debug: debug@fd904000 {
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compatible = "rockchip,debug";
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reg = <0x0 0xfd904000 0x0 0x1000>,
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<0x0 0xfd905000 0x0 0x1000>,
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<0x0 0xfd906000 0x0 0x1000>,
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<0x0 0xfd907000 0x0 0x1000>;
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};
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cspmu: cspmu@fd90c000 {
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compatible = "rockchip,cspmu";
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reg = <0x0 0xfd90c000 0x0 0x1000>,
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<0x0 0xfd90d000 0x0 0x1000>,
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<0x0 0xfd90e000 0x0 0x1000>,
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<0x0 0xfd90f000 0x0 0x1000>;
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};
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};
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&reserved_memory {
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ramoops: ramoops@110000 {
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compatible = "ramoops";
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reg = <0x0 0x110000 0x0 0xf0000>;
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record-size = <0x20000>;
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console-size = <0x80000>;
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ftrace-size = <0x00000>;
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pmsg-size = <0x50000>;
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};
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};
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&rng {
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status = "okay";
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};
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