// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Rockchip Electronics Co., Ltd.
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*
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*/
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/dts-v1/;
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#include "rk3399-box.dtsi"
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/ {
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model = "Rockchip RK3399 Board rev2 (BOX)";
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compatible = "rockchip-box-rev2","rockchip,rk3399-box";
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};
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&pinctrl {
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pinctrl-names = "default";
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pinctrl-0 = <&cpt_gpio>;
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sdio0 {
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sdio0_bus1: sdio0-bus1 {
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rockchip,pins =
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<2 RK_PC4 1 &pcfg_pull_up_20ma>;
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};
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sdio0_bus4: sdio0-bus4 {
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rockchip,pins =
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<2 RK_PC4 1 &pcfg_pull_up_20ma>,
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<2 RK_PC5 1 &pcfg_pull_up_20ma>,
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<2 RK_PC6 1 &pcfg_pull_up_20ma>,
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<2 RK_PC7 1 &pcfg_pull_up_20ma>;
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};
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sdio0_cmd: sdio0-cmd {
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rockchip,pins =
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<2 RK_PD0 1 &pcfg_pull_up_20ma>;
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};
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sdio0_clk: sdio0-clk {
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rockchip,pins =
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<2 RK_PD1 1 &pcfg_pull_none_20ma>;
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};
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};
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sdmmc {
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sdmmc_bus1: sdmmc-bus1 {
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rockchip,pins =
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<4 RK_PB0 1 &pcfg_pull_up_8ma>;
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};
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sdmmc_bus4: sdmmc-bus4 {
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rockchip,pins =
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<4 RK_PB0 1 &pcfg_pull_up_8ma>,
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<4 RK_PB1 1 &pcfg_pull_up_8ma>,
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<4 RK_PB2 1 &pcfg_pull_up_8ma>,
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<4 RK_PB3 1 &pcfg_pull_up_8ma>;
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};
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sdmmc_clk: sdmmc-clk {
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rockchip,pins =
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<4 RK_PB4 1 &pcfg_pull_none_18ma>;
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};
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sdmmc_cmd: sdmmc-cmd {
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rockchip,pins =
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<4 RK_PB5 1 &pcfg_pull_up_8ma>;
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};
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};
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fusb30x {
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fusb0_int: fusb0-int {
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rockchip,pins =
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<1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>;
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};
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};
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compat {
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cpt_gpio: cpt-gpio {
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rockchip,pins =
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<1 RK_PC2 RK_FUNC_GPIO &pcfg_output_low>;
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};
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};
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};
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&i2c4 {
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status = "okay";
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fusb0: fusb30x@22 {
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compatible = "fairchild,fusb302";
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reg = <0x22>;
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pinctrl-names = "default";
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pinctrl-0 = <&fusb0_int>;
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vbus-5v-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
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int-n-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
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status = "okay";
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};
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};
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&cdn_dp {
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status = "okay";
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extcon = <&fusb0>;
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};
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&hdmi_in_vopl {
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status = "disabled";
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};
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&dp_in_vopb {
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status = "disabled";
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};
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&route_hdmi {
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status = "okay";
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};
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&hdmi {
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status = "okay";
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rockchip,phy-table =
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<74250000 0x8009 0x0004 0x0272>,
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<165000000 0x802b 0x0004 0x0209>,
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<297000000 0x8039 0x0005 0x028d>,
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<594000000 0x8039 0x0000 0x019d>,
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<000000000 0x0000 0x0000 0x0000>;
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};
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