// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*/
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/dts-v1/;
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#include "rk3326.dtsi"
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#include "rk3326-linux.dtsi"
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#include "rk3326-evb-lp3-v10.dtsi"
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/ {
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model = "Rockchip rk3326 evb lpddr3 v10 board for linux";
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compatible = "rockchip,rk3326-evb-lp3-v10-linux", "rockchip,rk3326";
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chosen {
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bootargs = "earlycon=uart8250,mmio32,0xff160000 console=ttyFIQ0 rw root=PARTUUID=614e0000-0000 rootfstype=ext4 rootwait";
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};
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/delete-node/ test-power;
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};
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&cif_new {
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status = "okay";
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port {
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cif_in: endpoint {
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remote-endpoint = <&gc2155_out>;
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vsync-active = <0>;
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hsync-active = <1>;
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};
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};
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};
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&i2c2 {
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status = "okay";
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clock-frequency = <400000>;
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/* 24M mclk is shared for multiple cameras */
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pinctrl-0 = <&i2c2_xfer &cif_clkout_m0>;
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/* These are relatively safe rise/fall times; TODO: measure */
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i2c-scl-falling-time-ns = <50>;
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i2c-scl-rising-time-ns = <300>;
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gc2155: gc2155@3c {
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compatible = "gc,gc2155";
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reg = <0x3c>;
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pinctrl-names = "default";
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pinctrl-0 = <&cif_pin_m0>;
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clocks = <&cru SCLK_CIF_OUT>;
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clock-names = "xvclk";
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avdd-supply = <&vcc2v8_dvp>;
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dovdd-supply = <&vcc1v8_dvp>;
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dvdd-supply = <&vcc1v8_dvp>;
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/* hw changed the pwdn to gpio2_b5 */
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pwdn-gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
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port {
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gc2155_out: endpoint {
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remote-endpoint = <&cif_in>;
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};
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};
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};
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ov5695: ov5695@36 {
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compatible = "ovti,ov5695";
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reg = <0x36>;
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clocks = <&cru SCLK_CIF_OUT>;
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clock-names = "xvclk";
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avdd-supply = <&vcc2v8_dvp>;
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dovdd-supply = <&vcc1v8_dvp>;
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dvdd-supply = <&vdd1v5_dvp>;
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/*reset-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;*/
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pwdn-gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>;
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rockchip,camera-module-index = <0>;
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rockchip,camera-module-facing = "back";
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rockchip,camera-module-name = "TongJu";
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rockchip,camera-module-lens-name = "CHT842-MD";
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port {
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ucam_out: endpoint {
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remote-endpoint = <&mipi_in_ucam>;
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data-lanes = <1 2>;
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};
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};
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};
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};
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&mipi_dphy_rx0 {
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status = "okay";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <0>;
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mipi_in_ucam: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&ucam_out>;
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data-lanes = <1 2>;
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};
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};
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port@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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dphy_rx0_out: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&isp0_mipi_in>;
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};
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};
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};
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};
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&pinctrl {
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cif-pin-m0 {
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cif_pin_m0: cif-pin-m0 {
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rockchip,pins =
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<2 RK_PA0 1 &pcfg_pull_none>,/* cif_data2 */
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<2 RK_PA1 1 &pcfg_pull_none>,/* cif_data3 */
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<2 RK_PA2 1 &pcfg_pull_none>,/* cif_data4 */
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<2 RK_PA3 1 &pcfg_pull_none>,/* cif_data5 */
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<2 RK_PA4 1 &pcfg_pull_none>,/* cif_data6 */
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<2 RK_PA5 1 &pcfg_pull_none>,/* cif_data7 */
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<2 RK_PA6 1 &pcfg_pull_none>,/* cif_data8 */
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<2 RK_PA7 1 &pcfg_pull_none>,/* cif_data9 */
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<2 RK_PB0 1 &pcfg_pull_none>,/* cif_sync */
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<2 RK_PB1 1 &pcfg_pull_none>,/* cif_href */
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<2 RK_PB2 1 &pcfg_pull_none>;/* cif_clkin */
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};
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};
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};
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&rkisp1 {
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status = "okay";
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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isp0_mipi_in: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&dphy_rx0_out>;
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};
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};
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};
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&vip_mmu {
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status = "okay";
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};
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