// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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#include <dt-bindings/soc/rockchip-amp.h>
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/ {
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rockchip_amp: rockchip-amp {
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compatible = "rockchip,amp";
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clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>,
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<&cru PCLK_TIMER>, <&cru SCLK_TIMER4>, <&cru SCLK_TIMER5>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_xfer>;
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status = "okay";
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amp-cpu-aff-maskbits = /bits/ 64 <0x0 0x1 0x1 0x2 0x2 0x4 0x3 0x8>;
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amp-irqs = /bits/ 64 <GIC_AMP_IRQ_CFG_ROUTE(51, 0xd0, CPU_GET_AFFINITY(3, 0))
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GIC_AMP_IRQ_CFG_ROUTE(132, 0xd0, CPU_GET_AFFINITY(3, 0))>;
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};
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* remote amp core address */
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amp_reserved: amp@2e00000 {
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reg = <0x0 0x2e00000 0x0 0x1200000>;
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no-map;
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};
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rpmsg_reserved: rpmsg@7c00000 {
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reg = <0x0 0x07c00000 0x0 0x400000>;
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no-map;
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};
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rpmsg_dma_reserved: rpmsg-dma@8000000 {
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compatible = "shared-dma-pool";
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reg = <0x0 0x08000000 0x0 0x100000>;
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no-map;
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};
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};
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rpmsg: rpmsg@7c00000 {
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compatible = "rockchip,rpmsg-softirq";
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
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rockchip,vdev-nums = <1>;
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rockchip,link-id = <0x03>;
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reg = <0x0 0x7c00000 0x0 0x20000>;
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memory-region = <&rpmsg_dma_reserved>;
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status = "okay";
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};
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};
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&cpu3 {
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status = "disabled";
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};
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