/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* arch/arm/mach-tegra/sleep.S
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*
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* Copyright (c) 2010-2011, NVIDIA Corporation.
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* Copyright (c) 2011, Google, Inc.
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*
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* Author: Colin Cross <ccross@android.com>
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* Gary King <gking@nvidia.com>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <asm/cache.h>
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#include <asm/cp15.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "iomap.h"
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#include "sleep.h"
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#define CLK_RESET_CCLK_BURST 0x20
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#define CLK_RESET_CCLK_DIVIDER 0x24
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#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
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/*
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* tegra_disable_clean_inv_dcache
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*
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* disable, clean & invalidate the D-cache
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*
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* Corrupted registers: r1-r3, r6, r8, r9-r11
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*/
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ENTRY(tegra_disable_clean_inv_dcache)
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stmfd sp!, {r0, r4-r5, r7, r9-r11, lr}
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dmb @ ensure ordering
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/* Disable the D-cache */
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mrc p15, 0, r2, c1, c0, 0
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tst r2, #CR_C @ see tegra_sleep_cpu()
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bic r2, r2, #CR_C
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mcrne p15, 0, r2, c1, c0, 0
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isb
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/* Flush the D-cache */
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cmp r0, #TEGRA_FLUSH_CACHE_ALL
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blne v7_flush_dcache_louis
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bleq v7_flush_dcache_all
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/* Trun off coherency */
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exit_smp r4, r5
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ldmfd sp!, {r0, r4-r5, r7, r9-r11, pc}
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ENDPROC(tegra_disable_clean_inv_dcache)
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#endif
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#ifdef CONFIG_PM_SLEEP
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/*
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* tegra_init_l2_for_a15
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*
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* set up the correct L2 cache data RAM latency
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*/
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ENTRY(tegra_init_l2_for_a15)
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mrc p15, 0, r0, c0, c0, 5
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ubfx r0, r0, #8, #4
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tst r0, #1 @ only need for cluster 0
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bne _exit_init_l2_a15
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mrc p15, 0x1, r0, c9, c0, 2
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and r0, r0, #7
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cmp r0, #2
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bicne r0, r0, #7
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orrne r0, r0, #2
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mcrne p15, 0x1, r0, c9, c0, 2
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_exit_init_l2_a15:
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ret lr
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ENDPROC(tegra_init_l2_for_a15)
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/*
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* tegra_sleep_cpu_finish(unsigned long v2p)
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*
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* enters suspend in LP2 by turning off the mmu and jumping to
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* tegra?_tear_down_cpu
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*/
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ENTRY(tegra_sleep_cpu_finish)
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mov r4, r0
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/* Flush and disable the L1 data cache */
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mov r0, #TEGRA_FLUSH_CACHE_ALL
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bl tegra_disable_clean_inv_dcache
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mov r0, r4
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mov32 r6, tegra_tear_down_cpu
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ldr r1, [r6]
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add r1, r1, r0
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mov32 r3, tegra_shut_off_mmu
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add r3, r3, r0
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mov r0, r1
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ret r3
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ENDPROC(tegra_sleep_cpu_finish)
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/*
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* tegra_shut_off_mmu
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*
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* r0 = physical address to jump to with mmu off
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*
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* called with VA=PA mapping
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* turns off MMU, icache, dcache and branch prediction
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*/
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.align L1_CACHE_SHIFT
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.pushsection .idmap.text, "ax"
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ENTRY(tegra_shut_off_mmu)
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mrc p15, 0, r3, c1, c0, 0
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movw r2, #CR_I | CR_Z | CR_C | CR_M
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bic r3, r3, r2
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dsb
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mcr p15, 0, r3, c1, c0, 0
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isb
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#ifdef CONFIG_CACHE_L2X0
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/* Disable L2 cache */
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check_cpu_part_num 0xc09, r9, r10
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retne r0
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mov32 r2, TEGRA_ARM_PERIF_BASE + 0x3000
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ldr r3, [r2, #L2X0_CTRL]
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tst r3, #L2X0_CTRL_EN @ see tegra_sleep_cpu()
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mov r3, #0
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strne r3, [r2, #L2X0_CTRL]
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#endif
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ret r0
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ENDPROC(tegra_shut_off_mmu)
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.popsection
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/*
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* tegra_switch_cpu_to_pllp
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*
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* In LP2 the normal cpu clock pllx will be turned off. Switch the CPU to pllp
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*/
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ENTRY(tegra_switch_cpu_to_pllp)
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/* in LP2 idle (SDRAM active), set the CPU burst policy to PLLP */
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mov32 r5, TEGRA_CLK_RESET_BASE
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mov r0, #(2 << 28) @ burst policy = run mode
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orr r0, r0, #(4 << 4) @ use PLLP in run mode burst
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str r0, [r5, #CLK_RESET_CCLK_BURST]
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mov r0, #0
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str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
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ret lr
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ENDPROC(tegra_switch_cpu_to_pllp)
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#endif
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