// SPDX-License-Identifier: GPL-2.0-only
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/*
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* arch/arm/mach-sti/platsmp.c
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*
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* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
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* http://www.st.com
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*
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* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
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*
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* Copyright (C) 2002 ARM Ltd.
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* All Rights Reserved
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*/
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#include <linux/init.h>
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#include <linux/errno.h>
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#include <linux/delay.h>
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#include <linux/smp.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/memblock.h>
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#include <asm/cacheflush.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include "smp.h"
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static u32 __iomem *cpu_strt_ptr;
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static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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unsigned long entry_pa = __pa_symbol(secondary_startup);
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/*
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* Secondary CPU is initialised and started by a U-BOOTROM firmware.
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* Secondary CPU is spinning and waiting for a write at cpu_strt_ptr.
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* Writing secondary_startup address at cpu_strt_ptr makes it to
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* jump directly to secondary_startup().
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*/
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__raw_writel(entry_pa, cpu_strt_ptr);
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/* wmb so that data is actually written before cache flush is done */
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smp_wmb();
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sync_cache_w(cpu_strt_ptr);
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return 0;
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}
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static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
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{
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struct device_node *np;
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void __iomem *scu_base;
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u32 release_phys;
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int cpu;
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np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
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if (np) {
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scu_base = of_iomap(np, 0);
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scu_enable(scu_base);
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of_node_put(np);
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}
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if (max_cpus <= 1)
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return;
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for_each_possible_cpu(cpu) {
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np = of_get_cpu_node(cpu, NULL);
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if (!np)
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continue;
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if (of_property_read_u32(np, "cpu-release-addr",
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&release_phys)) {
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pr_err("CPU %d: missing or invalid cpu-release-addr "
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"property\n", cpu);
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continue;
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}
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/*
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* cpu-release-addr is usually configured in SBC DMEM but can
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* also be in RAM.
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*/
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if (!memblock_is_memory(release_phys))
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cpu_strt_ptr =
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ioremap(release_phys, sizeof(release_phys));
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else
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cpu_strt_ptr =
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(u32 __iomem *)phys_to_virt(release_phys);
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set_cpu_possible(cpu, true);
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}
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}
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const struct smp_operations sti_smp_ops __initconst = {
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.smp_prepare_cpus = sti_smp_prepare_cpus,
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.smp_boot_secondary = sti_boot_secondary,
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};
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