// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2012-2015 Altera Corporation
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*/
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#include <linux/irqchip.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/reboot.h>
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#include <linux/reset/socfpga.h>
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#include <asm/hardware/cache-l2x0.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/map.h>
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#include <asm/cacheflush.h>
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#include "core.h"
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void __iomem *sys_manager_base_addr;
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void __iomem *rst_manager_base_addr;
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void __iomem *sdr_ctl_base_addr;
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unsigned long socfpga_cpu1start_addr;
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static void __init socfpga_sysmgr_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "altr,sys-mgr");
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if (of_property_read_u32(np, "cpu1-start-addr",
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(u32 *) &socfpga_cpu1start_addr))
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pr_err("SMP: Need cpu1-start-addr in device tree.\n");
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/* Ensure that socfpga_cpu1start_addr is visible to other CPUs */
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smp_wmb();
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sync_cache_w(&socfpga_cpu1start_addr);
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sys_manager_base_addr = of_iomap(np, 0);
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np = of_find_compatible_node(NULL, NULL, "altr,rst-mgr");
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rst_manager_base_addr = of_iomap(np, 0);
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np = of_find_compatible_node(NULL, NULL, "altr,sdr-ctl");
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sdr_ctl_base_addr = of_iomap(np, 0);
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}
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static void __init socfpga_init_irq(void)
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{
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irqchip_init();
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socfpga_sysmgr_init();
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if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
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socfpga_init_l2_ecc();
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if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
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socfpga_init_ocram_ecc();
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socfpga_reset_init();
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}
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static void __init socfpga_arria10_init_irq(void)
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{
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irqchip_init();
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socfpga_sysmgr_init();
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if (IS_ENABLED(CONFIG_EDAC_ALTERA_L2C))
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socfpga_init_arria10_l2_ecc();
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if (IS_ENABLED(CONFIG_EDAC_ALTERA_OCRAM))
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socfpga_init_arria10_ocram_ecc();
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socfpga_reset_init();
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}
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static void socfpga_cyclone5_restart(enum reboot_mode mode, const char *cmd)
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{
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u32 temp;
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temp = readl(rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
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if (mode == REBOOT_WARM)
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temp |= RSTMGR_CTRL_SWWARMRSTREQ;
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else
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temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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writel(temp, rst_manager_base_addr + SOCFPGA_RSTMGR_CTRL);
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}
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static void socfpga_arria10_restart(enum reboot_mode mode, const char *cmd)
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{
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u32 temp;
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temp = readl(rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
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if (mode == REBOOT_WARM)
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temp |= RSTMGR_CTRL_SWWARMRSTREQ;
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else
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temp |= RSTMGR_CTRL_SWCOLDRSTREQ;
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writel(temp, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_CTRL);
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}
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static const char *altera_dt_match[] = {
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"altr,socfpga",
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NULL
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};
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DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = socfpga_init_irq,
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.restart = socfpga_cyclone5_restart,
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.dt_compat = altera_dt_match,
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MACHINE_END
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static const char *altera_a10_dt_match[] = {
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"altr,socfpga-arria10",
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NULL
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};
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DT_MACHINE_START(SOCFPGA_A10, "Altera SOCFPGA Arria10")
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.l2c_aux_val = 0,
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.l2c_aux_mask = ~0,
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.init_irq = socfpga_arria10_init_irq,
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.restart = socfpga_arria10_restart,
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.dt_compat = altera_a10_dt_match,
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MACHINE_END
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