/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright 2012 Pavel Machek <pavel@denx.de>
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* Copyright (C) 2012-2015 Altera Corporation
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*/
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#ifndef __MACH_CORE_H
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#define __MACH_CORE_H
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#define SOCFPGA_RSTMGR_CTRL 0x04
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#define SOCFPGA_RSTMGR_MODMPURST 0x10
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#define SOCFPGA_RSTMGR_MODPERRST 0x14
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#define SOCFPGA_RSTMGR_BRGMODRST 0x1c
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#define SOCFPGA_A10_RSTMGR_CTRL 0xC
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#define SOCFPGA_A10_RSTMGR_MODMPURST 0x20
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/* System Manager bits */
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#define RSTMGR_CTRL_SWCOLDRSTREQ 0x1 /* Cold Reset */
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#define RSTMGR_CTRL_SWWARMRSTREQ 0x2 /* Warm Reset */
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#define RSTMGR_MPUMODRST_CPU1 0x2 /* CPU1 Reset */
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void socfpga_init_l2_ecc(void);
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void socfpga_init_ocram_ecc(void);
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void socfpga_init_arria10_l2_ecc(void);
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void socfpga_init_arria10_ocram_ecc(void);
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extern void __iomem *sys_manager_base_addr;
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extern void __iomem *rst_manager_base_addr;
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extern void __iomem *sdr_ctl_base_addr;
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u32 socfpga_sdram_self_refresh(u32 sdr_base);
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extern unsigned int socfpga_sdram_self_refresh_sz;
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extern char secondary_trampoline[], secondary_trampoline_end[];
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extern unsigned long socfpga_cpu1start_addr;
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#define SOCFPGA_SCU_VIRT_BASE 0xfee00000
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#endif
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