/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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#ifndef RKPM_HELPERS_H
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#define RKPM_HELPERS_H
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#define REG_MSK_SHIFT 16
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#ifndef BIT
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#define BIT(nr) (1U << (nr))
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#endif
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#ifndef WMSK_BIT
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#define WMSK_BIT(nr) BIT((nr) + REG_MSK_SHIFT)
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#endif
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/* set one bit with write mask */
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#ifndef BIT_WITH_WMSK
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#define BIT_WITH_WMSK(nr) (BIT(nr) | WMSK_BIT(nr))
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#endif
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#ifndef BITS_SHIFT
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#define BITS_SHIFT(bits, shift) ((bits) << (shift))
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#endif
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#ifndef BITS_WMSK
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#define BITS_WMSK(msk, shift) \
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((msk) << ((shift) + REG_MSK_SHIFT))
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#endif
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#ifndef BITS_WITH_WMASK
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#define BITS_WITH_WMASK(bits, msk, shift) \
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(BITS_SHIFT(bits, shift) | BITS_SHIFT(msk, ((shift) + REG_MSK_SHIFT)))
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#endif
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#ifndef BIT_SET_WMSK
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#define BIT_SET_WMSK(nr) BIT_WITH_WMSK(nr)
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#endif
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#ifndef BIT_CLR_WMSK
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#define BIT_CLR_WMSK(nr) WMSK_BIT(nr)
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#endif
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#ifndef WITH_16BITS_WMSK
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#define WITH_16BITS_WMSK(bits) (0xffff0000 | (bits))
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#endif
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#define REG_REGION(_start, _end, _stride, _base, _wmsk) \
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.start = (_start), \
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.end = (_end), \
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.stride = (_stride), \
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.wmsk = (_wmsk), \
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.base = (_base),
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struct reg_region {
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void __iomem **base;
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u32 start;
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u32 end;
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u32 stride;
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u32 wmsk;
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u32 *buf;
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};
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void rkpm_alloc_region_mem(struct reg_region *rgns, u32 rgn_num);
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void rkpm_region_mem_init(u32 size);
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void rkpm_reg_rgn_save(struct reg_region *rgns, u32 rgn_num);
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void rkpm_reg_rgn_restore(struct reg_region *rgns, u32 rgn_num);
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void rkpm_reg_rgn_restore_reverse(struct reg_region *rgns, u32 rgn_num);
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void rkpm_dump_reg_rgns(struct reg_region *rgns, u32 rgn_num);
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void rkpm_printch(int c);
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void rkpm_printstr(const char *s);
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void rkpm_printhex(u32 hex);
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void rkpm_printdec(int dec);
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void rkpm_regs_dump(void __iomem *base,
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u32 start_offset,
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u32 end_offset,
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u32 stride);
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void rkpm_raw_udelay(int us);
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#endif
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