/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2023 Rockchip Electronics Co., Ltd.
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*/
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#ifndef RKPM_GICV2_H
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#define RKPM_GICV2_H
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struct plat_gicv2_dist_ctx_t {
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u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
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u32 saved_spi_prio[DIV_ROUND_UP(1020, 4)];
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u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
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u32 saved_spi_grp[DIV_ROUND_UP(1020, 32)];
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u32 saved_spi_active[DIV_ROUND_UP(1020, 32)];
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u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
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u32 saved_gicd_ctrl;
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};
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struct plat_gicv2_cpu_ctx_t {
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u32 saved_ppi_enable;
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u32 saved_ppi_active;
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u32 saved_ppi_conf[DIV_ROUND_UP(32, 16)];
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u32 saved_ppi_prio[DIV_ROUND_UP(32, 4)];
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u32 saved_ppi_grp;
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u32 saved_gicc_ctrl;
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u32 saved_gicc_pmr;
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};
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void rkpm_gicv2_dist_save(void __iomem *dist_base,
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struct plat_gicv2_dist_ctx_t *ctx);
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void rkpm_gicv2_dist_restore(void __iomem *dist_base,
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struct plat_gicv2_dist_ctx_t *ctx);
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void rkpm_gicv2_cpu_save(void __iomem *dist_base,
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void __iomem *cpu_base,
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struct plat_gicv2_cpu_ctx_t *ctx);
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void rkpm_gicv2_cpu_restore(void __iomem *dist_base,
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void __iomem *cpu_base,
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struct plat_gicv2_cpu_ctx_t *ctx);
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#endif
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