/*
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* PXA27x standby mode
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*
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* Author: David Burrage
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*
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* 2005 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/hardware.h>
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#include <mach/pxa2xx-regs.h>
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.text
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#ifdef CONFIG_PXA27x
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ENTRY(pxa_cpu_standby)
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ldr r0, =PSSR
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mov r1, #(PSSR_PH | PSSR_STS)
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mov r2, #PWRMODE_STANDBY
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mov r3, #UNCACHED_PHYS_0 @ Read mem context in.
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ldr ip, [r3]
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b 1f
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.align 5
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1: mcr p14, 0, r2, c7, c0, 0 @ put the system into Standby
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str r1, [r0] @ make sure PSSR_PH/STS are clear
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ret lr
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#endif
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#ifdef CONFIG_PXA3xx
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#define PXA3_MDCNFG 0x0000
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#define PXA3_MDCNFG_DMCEN (1 << 30)
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#define PXA3_DDR_HCAL 0x0060
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#define PXA3_DDR_HCAL_HCRNG 0x1f
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#define PXA3_DDR_HCAL_HCPROG (1 << 28)
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#define PXA3_DDR_HCAL_HCEN (1 << 31)
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#define PXA3_DMCIER 0x0070
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#define PXA3_DMCIER_EDLP (1 << 29)
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#define PXA3_DMCISR 0x0078
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#define PXA3_RCOMP 0x0100
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#define PXA3_RCOMP_SWEVAL (1 << 31)
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ENTRY(pm_enter_standby_start)
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mov r1, #0xf6000000 @ DMEMC_REG_BASE (PXA3_MDCNFG)
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add r1, r1, #0x00100000
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/*
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* Preload the TLB entry for accessing the dynamic memory
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* controller registers. Note that page table lookups will
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* fail until the dynamic memory controller has been
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* reinitialised - and that includes MMU page table walks.
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* This also means that only the dynamic memory controller
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* can be reliably accessed in the code following standby.
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*/
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ldr r2, [r1] @ Dummy read PXA3_MDCNFG
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mcr p14, 0, r0, c7, c0, 0
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.rept 8
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nop
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.endr
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ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
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bic r0, r0, #PXA3_DDR_HCAL_HCEN
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str r0, [r1, #PXA3_DDR_HCAL]
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1: ldr r0, [r1, #PXA3_DDR_HCAL]
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tst r0, #PXA3_DDR_HCAL_HCEN
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bne 1b
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ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
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orr r0, r0, #PXA3_RCOMP_SWEVAL
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str r0, [r1, #PXA3_RCOMP]
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mov r0, #~0 @ Clear interrupts
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str r0, [r1, #PXA3_DMCISR]
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ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
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orr r0, r0, #PXA3_DMCIER_EDLP
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str r0, [r1, #PXA3_DMCIER]
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ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
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bic r0, r0, #PXA3_DDR_HCAL_HCRNG
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orr r0, r0, #PXA3_DDR_HCAL_HCEN | PXA3_DDR_HCAL_HCPROG
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str r0, [r1, #PXA3_DDR_HCAL]
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1: ldr r0, [r1, #PXA3_DMCISR]
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tst r0, #PXA3_DMCIER_EDLP
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beq 1b
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ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
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orr r0, r0, #PXA3_MDCNFG_DMCEN
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str r0, [r1, #PXA3_MDCNFG]
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1: ldr r0, [r1, #PXA3_MDCNFG]
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tst r0, #PXA3_MDCNFG_DMCEN
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beq 1b
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ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
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orr r0, r0, #2 @ HCRNG
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str r0, [r1, #PXA3_DDR_HCAL]
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ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt
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bic r0, r0, #0x20000000
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str r0, [r1, #PXA3_DMCIER]
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ret lr
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ENTRY(pm_enter_standby_end)
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#endif
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