/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* (C) Copyright 2007
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* Texas Instruments
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* Karthik Dasu <karthik-dp@ti.com>
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*
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* (C) Copyright 2004
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* Texas Instruments, <www.ti.com>
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* Richard Woodruff <r-woodruff2@ti.com>
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include "omap34xx.h"
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#include "iomap.h"
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#include "cm3xxx.h"
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#include "prm3xxx.h"
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#include "sdrc.h"
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#include "sram.h"
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#include "control.h"
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/*
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* Registers access definitions
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*/
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#define SDRC_SCRATCHPAD_SEM_OFFS 0xc
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#define SDRC_SCRATCHPAD_SEM_V OMAP343X_SCRATCHPAD_REGADDR\
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(SDRC_SCRATCHPAD_SEM_OFFS)
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#define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
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OMAP3430_PM_PREPWSTST
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#define PM_PWSTCTRL_MPU_P OMAP3430_PRM_BASE + MPU_MOD + OMAP2_PM_PWSTCTRL
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#define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
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#define CM_IDLEST_CKGEN_V OMAP34XX_CM_REGADDR(PLL_MOD, CM_IDLEST)
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#define SRAM_BASE_P OMAP3_SRAM_PA
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#define CONTROL_STAT OMAP343X_CTRL_BASE + OMAP343X_CONTROL_STATUS
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#define CONTROL_MEM_RTA_CTRL (OMAP343X_CTRL_BASE +\
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OMAP36XX_CONTROL_MEM_RTA_CTRL)
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/* Move this as correct place is available */
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#define SCRATCHPAD_MEM_OFFS 0x310
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#define SCRATCHPAD_BASE_P (OMAP343X_CTRL_BASE +\
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OMAP343X_CONTROL_MEM_WKUP +\
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SCRATCHPAD_MEM_OFFS)
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#define SDRC_POWER_V OMAP34XX_SDRC_REGADDR(SDRC_POWER)
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#define SDRC_SYSCONFIG_P (OMAP343X_SDRC_BASE + SDRC_SYSCONFIG)
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#define SDRC_MR_0_P (OMAP343X_SDRC_BASE + SDRC_MR_0)
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#define SDRC_EMR2_0_P (OMAP343X_SDRC_BASE + SDRC_EMR2_0)
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#define SDRC_MANUAL_0_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_0)
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#define SDRC_MR_1_P (OMAP343X_SDRC_BASE + SDRC_MR_1)
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#define SDRC_EMR2_1_P (OMAP343X_SDRC_BASE + SDRC_EMR2_1)
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#define SDRC_MANUAL_1_P (OMAP343X_SDRC_BASE + SDRC_MANUAL_1)
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#define SDRC_DLLA_STATUS_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_STATUS)
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#define SDRC_DLLA_CTRL_V OMAP34XX_SDRC_REGADDR(SDRC_DLLA_CTRL)
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/*
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* This file needs be built unconditionally as ARM to interoperate correctly
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* with non-Thumb-2-capable firmware.
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*/
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.arm
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/*
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* API functions
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*/
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.text
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/*
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* L2 cache needs to be toggled for stable OFF mode functionality on 3630.
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* This function sets up a flag that will allow for this toggling to take
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* place on 3630. Hopefully some version in the future may not need this.
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*/
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ENTRY(enable_omap3630_toggle_l2_on_restore)
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stmfd sp!, {lr} @ save registers on stack
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/* Setup so that we will disable and enable l2 */
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mov r1, #0x1
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adr r3, l2dis_3630_offset
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ldr r2, [r3] @ value for offset
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str r1, [r2, r3] @ write to l2dis_3630
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ldmfd sp!, {pc} @ restore regs and return
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ENDPROC(enable_omap3630_toggle_l2_on_restore)
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/*
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* Function to call rom code to save secure ram context.
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*
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* r0 = physical address of the parameters
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*/
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.arch armv7-a
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.arch_extension sec
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ENTRY(save_secure_ram_context)
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stmfd sp!, {r4 - r11, lr} @ save registers on stack
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mov r3, r0 @ physical address of parameters
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mov r0, #25 @ set service ID for PPA
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mov r12, r0 @ copy secure service ID in r12
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mov r1, #0 @ set task id for ROM code in r1
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mov r2, #4 @ set some flags in r2, r6
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mov r6, #0xff
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dsb @ data write barrier
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dmb @ data memory barrier
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smc #1 @ call SMI monitor (smi #1)
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nop
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nop
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nop
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nop
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ldmfd sp!, {r4 - r11, pc}
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ENDPROC(save_secure_ram_context)
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/*
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* ======================
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* == Idle entry point ==
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* ======================
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*/
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/*
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* Forces OMAP into idle state
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*
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* omap34xx_cpu_suspend() - This bit of code saves the CPU context if needed
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* and executes the WFI instruction. Calling WFI effectively changes the
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* power domains states to the desired target power states.
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*
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*
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* Notes:
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* - only the minimum set of functions gets copied to internal SRAM at boot
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* and after wake-up from OFF mode, cf. omap_push_sram_idle. The function
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* pointers in SDRAM or SRAM are called depending on the desired low power
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* target state.
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* - when the OMAP wakes up it continues at different execution points
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* depending on the low power mode (non-OFF vs OFF modes),
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* cf. 'Resume path for xxx mode' comments.
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*/
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.align 3
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ENTRY(omap34xx_cpu_suspend)
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stmfd sp!, {r4 - r11, lr} @ save registers on stack
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/*
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* r0 contains information about saving context:
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* 0 - No context lost
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* 1 - Only L1 and logic lost
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* 2 - Only L2 lost (Even L1 is retained we clean it along with L2)
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* 3 - Both L1 and L2 lost and logic lost
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*/
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/*
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* For OFF mode: save context and jump to WFI in SDRAM (omap3_do_wfi)
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* For non-OFF modes: jump to the WFI code in SRAM (omap3_do_wfi_sram)
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*/
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ldr r4, omap3_do_wfi_sram_addr
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ldr r5, [r4]
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cmp r0, #0x0 @ If no context save required,
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bxeq r5 @ jump to the WFI code in SRAM
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/* Otherwise fall through to the save context code */
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save_context_wfi:
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/*
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* jump out to kernel flush routine
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* - reuse that code is better
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* - it executes in a cached space so is faster than refetch per-block
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* - should be faster and will change with kernel
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* - 'might' have to copy address, load and jump to it
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* Flush all data from the L1 data cache before disabling
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* SCTLR.C bit.
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*/
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ldr r1, kernel_flush
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mov lr, pc
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bx r1
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/*
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* Clear the SCTLR.C bit to prevent further data cache
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* allocation. Clearing SCTLR.C would make all the data accesses
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* strongly ordered and would not hit the cache.
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*/
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mrc p15, 0, r0, c1, c0, 0
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bic r0, r0, #(1 << 2) @ Disable the C bit
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mcr p15, 0, r0, c1, c0, 0
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isb
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/*
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* Invalidate L1 data cache. Even though only invalidate is
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* necessary exported flush API is used here. Doing clean
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* on already clean cache would be almost NOP.
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*/
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ldr r1, kernel_flush
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blx r1
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b omap3_do_wfi
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ENDPROC(omap34xx_cpu_suspend)
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omap3_do_wfi_sram_addr:
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.word omap3_do_wfi_sram
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kernel_flush:
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.word v7_flush_dcache_all
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/* ===================================
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* == WFI instruction => Enter idle ==
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* ===================================
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*/
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/*
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* Do WFI instruction
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* Includes the resume path for non-OFF modes
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*
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* This code gets copied to internal SRAM and is accessible
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* from both SDRAM and SRAM:
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* - executed from SRAM for non-off modes (omap3_do_wfi_sram),
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* - executed from SDRAM for OFF mode (omap3_do_wfi).
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*/
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.align 3
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ENTRY(omap3_do_wfi)
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ldr r4, sdrc_power @ read the SDRC_POWER register
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ldr r5, [r4] @ read the contents of SDRC_POWER
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orr r5, r5, #0x40 @ enable self refresh on idle req
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str r5, [r4] @ write back to SDRC_POWER register
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/* Data memory barrier and Data sync barrier */
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dsb
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dmb
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/*
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* ===================================
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* == WFI instruction => Enter idle ==
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* ===================================
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*/
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wfi @ wait for interrupt
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/*
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* ===================================
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* == Resume path for non-OFF modes ==
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* ===================================
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*/
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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/*
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* This function implements the erratum ID i581 WA:
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* SDRC state restore before accessing the SDRAM
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*
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* Only used at return from non-OFF mode. For OFF
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* mode the ROM code configures the SDRC and
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* the DPLL before calling the restore code directly
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* from DDR.
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*/
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/* Make sure SDRC accesses are ok */
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wait_sdrc_ok:
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/* DPLL3 must be locked before accessing the SDRC. Maybe the HW ensures this */
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ldr r4, cm_idlest_ckgen
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wait_dpll3_lock:
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ldr r5, [r4]
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tst r5, #1
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beq wait_dpll3_lock
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ldr r4, cm_idlest1_core
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wait_sdrc_ready:
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ldr r5, [r4]
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tst r5, #0x2
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bne wait_sdrc_ready
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/* allow DLL powerdown upon hw idle req */
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ldr r4, sdrc_power
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ldr r5, [r4]
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bic r5, r5, #0x40
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str r5, [r4]
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is_dll_in_lock_mode:
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/* Is dll in lock mode? */
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ldr r4, sdrc_dlla_ctrl
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ldr r5, [r4]
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tst r5, #0x4
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bne exit_nonoff_modes @ Return if locked
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/* wait till dll locks */
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wait_dll_lock_timed:
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ldr r4, sdrc_dlla_status
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/* Wait 20uS for lock */
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mov r6, #8
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wait_dll_lock:
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subs r6, r6, #0x1
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beq kick_dll
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ldr r5, [r4]
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and r5, r5, #0x4
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cmp r5, #0x4
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bne wait_dll_lock
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b exit_nonoff_modes @ Return when locked
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/* disable/reenable DLL if not locked */
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kick_dll:
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ldr r4, sdrc_dlla_ctrl
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ldr r5, [r4]
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mov r6, r5
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bic r6, #(1<<3) @ disable dll
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str r6, [r4]
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dsb
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orr r6, r6, #(1<<3) @ enable dll
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str r6, [r4]
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dsb
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b wait_dll_lock_timed
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exit_nonoff_modes:
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/* Re-enable C-bit if needed */
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mrc p15, 0, r0, c1, c0, 0
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tst r0, #(1 << 2) @ Check C bit enabled?
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orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
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mcreq p15, 0, r0, c1, c0, 0
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isb
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/*
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* ===================================
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* == Exit point from non-OFF modes ==
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* ===================================
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*/
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ldmfd sp!, {r4 - r11, pc} @ restore regs and return
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ENDPROC(omap3_do_wfi)
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sdrc_power:
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.word SDRC_POWER_V
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cm_idlest1_core:
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.word CM_IDLEST1_CORE_V
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cm_idlest_ckgen:
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.word CM_IDLEST_CKGEN_V
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sdrc_dlla_status:
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.word SDRC_DLLA_STATUS_V
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sdrc_dlla_ctrl:
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.word SDRC_DLLA_CTRL_V
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ENTRY(omap3_do_wfi_sz)
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.word . - omap3_do_wfi
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/*
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* ==============================
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* == Resume path for OFF mode ==
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* ==============================
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*/
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/*
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* The restore_* functions are called by the ROM code
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* when back from WFI in OFF mode.
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* Cf. the get_*restore_pointer functions.
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*
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* restore_es3: applies to 34xx >= ES3.0
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* restore_3630: applies to 36xx
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* restore: common code for 3xxx
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*
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* Note: when back from CORE and MPU OFF mode we are running
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* from SDRAM, without MMU, without the caches and prediction.
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* Also the SRAM content has been cleared.
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*/
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ENTRY(omap3_restore_es3)
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ldr r5, pm_prepwstst_core_p
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ldr r4, [r5]
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and r4, r4, #0x3
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cmp r4, #0x0 @ Check if previous power state of CORE is OFF
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bne omap3_restore @ Fall through to OMAP3 common code
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adr r0, es3_sdrc_fix
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ldr r1, sram_base
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ldr r2, es3_sdrc_fix_sz
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mov r2, r2, ror #2
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copy_to_sram:
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ldmia r0!, {r3} @ val = *src
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stmia r1!, {r3} @ *dst = val
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subs r2, r2, #0x1 @ num_words--
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bne copy_to_sram
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ldr r1, sram_base
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blx r1
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b omap3_restore @ Fall through to OMAP3 common code
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ENDPROC(omap3_restore_es3)
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ENTRY(omap3_restore_3630)
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ldr r1, pm_prepwstst_core_p
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ldr r2, [r1]
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and r2, r2, #0x3
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cmp r2, #0x0 @ Check if previous power state of CORE is OFF
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bne omap3_restore @ Fall through to OMAP3 common code
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/* Disable RTA before giving control */
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ldr r1, control_mem_rta
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mov r2, #OMAP36XX_RTA_DISABLE
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str r2, [r1]
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ENDPROC(omap3_restore_3630)
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/* Fall through to common code for the remaining logic */
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ENTRY(omap3_restore)
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/*
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* Read the pwstctrl register to check the reason for mpu reset.
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* This tells us what was lost.
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*/
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ldr r1, pm_pwstctrl_mpu
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ldr r2, [r1]
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and r2, r2, #0x3
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cmp r2, #0x0 @ Check if target power state was OFF or RET
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bne logic_l1_restore
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adr r1, l2dis_3630_offset @ address for offset
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ldr r0, [r1] @ value for offset
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ldr r0, [r1, r0] @ value at l2dis_3630
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cmp r0, #0x1 @ should we disable L2 on 3630?
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bne skipl2dis
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mrc p15, 0, r0, c1, c0, 1
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bic r0, r0, #2 @ disable L2 cache
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mcr p15, 0, r0, c1, c0, 1
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skipl2dis:
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ldr r0, control_stat
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ldr r1, [r0]
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and r1, #0x700
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cmp r1, #0x300
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beq l2_inv_gp
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adr r0, l2_inv_api_params_offset
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ldr r3, [r0]
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add r3, r3, r0 @ r3 points to dummy parameters
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mov r0, #40 @ set service ID for PPA
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mov r12, r0 @ copy secure Service ID in r12
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mov r1, #0 @ set task id for ROM code in r1
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mov r2, #4 @ set some flags in r2, r6
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mov r6, #0xff
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dsb @ data write barrier
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dmb @ data memory barrier
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smc #1 @ call SMI monitor (smi #1)
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/* Write to Aux control register to set some bits */
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mov r0, #42 @ set service ID for PPA
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mov r12, r0 @ copy secure Service ID in r12
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mov r1, #0 @ set task id for ROM code in r1
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mov r2, #4 @ set some flags in r2, r6
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mov r6, #0xff
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ldr r4, scratchpad_base
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ldr r3, [r4, #0xBC] @ r3 points to parameters
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dsb @ data write barrier
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dmb @ data memory barrier
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smc #1 @ call SMI monitor (smi #1)
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#ifdef CONFIG_OMAP3_L2_AUX_SECURE_SAVE_RESTORE
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/* Restore L2 aux control register */
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@ set service ID for PPA
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mov r0, #CONFIG_OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
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mov r12, r0 @ copy service ID in r12
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mov r1, #0 @ set task ID for ROM code in r1
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mov r2, #4 @ set some flags in r2, r6
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mov r6, #0xff
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ldr r4, scratchpad_base
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ldr r3, [r4, #0xBC]
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adds r3, r3, #8 @ r3 points to parameters
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dsb @ data write barrier
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dmb @ data memory barrier
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smc #1 @ call SMI monitor (smi #1)
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#endif
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b logic_l1_restore
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.align
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l2_inv_api_params_offset:
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.long l2_inv_api_params - .
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l2_inv_gp:
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/* Execute smi to invalidate L2 cache */
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mov r12, #0x1 @ set up to invalidate L2
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smc #0 @ Call SMI monitor (smieq)
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/* Write to Aux control register to set some bits */
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ldr r4, scratchpad_base
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ldr r3, [r4,#0xBC]
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ldr r0, [r3,#4]
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mov r12, #0x3
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smc #0 @ Call SMI monitor (smieq)
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ldr r4, scratchpad_base
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ldr r3, [r4,#0xBC]
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ldr r0, [r3,#12]
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mov r12, #0x2
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smc #0 @ Call SMI monitor (smieq)
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logic_l1_restore:
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adr r0, l2dis_3630_offset @ adress for offset
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ldr r1, [r0] @ value for offset
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ldr r1, [r0, r1] @ value at l2dis_3630
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cmp r1, #0x1 @ Test if L2 re-enable needed on 3630
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bne skipl2reen
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mrc p15, 0, r1, c1, c0, 1
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orr r1, r1, #2 @ re-enable L2 cache
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mcr p15, 0, r1, c1, c0, 1
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skipl2reen:
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/* Now branch to the common CPU resume function */
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b cpu_resume
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ENDPROC(omap3_restore)
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.ltorg
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/*
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* Local variables
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*/
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pm_prepwstst_core_p:
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.word PM_PREPWSTST_CORE_P
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pm_pwstctrl_mpu:
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.word PM_PWSTCTRL_MPU_P
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scratchpad_base:
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.word SCRATCHPAD_BASE_P
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sram_base:
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.word SRAM_BASE_P + 0x8000
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control_stat:
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.word CONTROL_STAT
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control_mem_rta:
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.word CONTROL_MEM_RTA_CTRL
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l2dis_3630_offset:
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.long l2dis_3630 - .
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.data
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.align 2
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l2dis_3630:
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.word 0
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.data
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.align 2
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l2_inv_api_params:
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.word 0x1, 0x00
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/*
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* Internal functions
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*/
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/*
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* This function implements the erratum ID i443 WA, applies to 34xx >= ES3.0
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* Copied to and run from SRAM in order to reconfigure the SDRC parameters.
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*/
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.text
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.align 3
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ENTRY(es3_sdrc_fix)
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ldr r4, sdrc_syscfg @ get config addr
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ldr r5, [r4] @ get value
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tst r5, #0x100 @ is part access blocked
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it eq
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biceq r5, r5, #0x100 @ clear bit if set
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str r5, [r4] @ write back change
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ldr r4, sdrc_mr_0 @ get config addr
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ldr r5, [r4] @ get value
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str r5, [r4] @ write back change
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ldr r4, sdrc_emr2_0 @ get config addr
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ldr r5, [r4] @ get value
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str r5, [r4] @ write back change
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ldr r4, sdrc_manual_0 @ get config addr
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mov r5, #0x2 @ autorefresh command
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str r5, [r4] @ kick off refreshes
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ldr r4, sdrc_mr_1 @ get config addr
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ldr r5, [r4] @ get value
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str r5, [r4] @ write back change
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ldr r4, sdrc_emr2_1 @ get config addr
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ldr r5, [r4] @ get value
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str r5, [r4] @ write back change
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ldr r4, sdrc_manual_1 @ get config addr
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mov r5, #0x2 @ autorefresh command
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str r5, [r4] @ kick off refreshes
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bx lr
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/*
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* Local variables
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*/
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.align
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sdrc_syscfg:
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.word SDRC_SYSCONFIG_P
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sdrc_mr_0:
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.word SDRC_MR_0_P
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sdrc_emr2_0:
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.word SDRC_EMR2_0_P
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sdrc_manual_0:
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.word SDRC_MANUAL_0_P
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sdrc_mr_1:
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.word SDRC_MR_1_P
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sdrc_emr2_1:
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.word SDRC_EMR2_1_P
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sdrc_manual_1:
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.word SDRC_MANUAL_1_P
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ENDPROC(es3_sdrc_fix)
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ENTRY(es3_sdrc_fix_sz)
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.word . - es3_sdrc_fix
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