/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* OMAP44xx Clock Management register bits
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*
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* Copyright (C) 2009-2012 Texas Instruments, Inc.
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* Copyright (C) 2009-2010 Nokia Corporation
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*
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* Paul Walmsley (paul@pwsan.com)
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* Rajendra Nayak (rnayak@ti.com)
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* Benoit Cousson (b-cousson@ti.com)
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*
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* This file is automatically generated from the OMAP hardware databases.
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* We respectfully ask that any modifications to this file be coordinated
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* with the public linux-omap@vger.kernel.org mailing list and the
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* authors above to ensure that the autogeneration scripts are kept
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* up-to-date with the file contents.
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*/
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#ifndef __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
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#define __ARCH_ARM_MACH_OMAP2_CM_REGBITS_44XX_H
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#define OMAP4430_ABE_STATDEP_SHIFT 3
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#define OMAP4430_AUTO_DPLL_MODE_MASK (0x7 << 0)
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#define OMAP4430_CLKSEL_SHIFT 24
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#define OMAP4430_CLKSEL_WIDTH 0x1
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#define OMAP4430_CLKSEL_MASK (1 << 24)
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#define OMAP4430_CLKSEL_0_0_SHIFT 0
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#define OMAP4430_CLKSEL_0_0_WIDTH 0x1
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#define OMAP4430_CLKSEL_0_1_SHIFT 0
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#define OMAP4430_CLKSEL_0_1_WIDTH 0x2
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#define OMAP4430_CLKSEL_24_25_SHIFT 24
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#define OMAP4430_CLKSEL_24_25_WIDTH 0x2
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#define OMAP4430_CLKSEL_60M_SHIFT 24
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#define OMAP4430_CLKSEL_60M_WIDTH 0x1
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#define OMAP4430_CLKSEL_AESS_FCLK_SHIFT 24
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#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH 0x1
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#define OMAP4430_CLKSEL_CORE_SHIFT 0
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#define OMAP4430_CLKSEL_CORE_WIDTH 0x1
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#define OMAP4430_CLKSEL_DIV_SHIFT 24
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#define OMAP4430_CLKSEL_DIV_WIDTH 0x1
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#define OMAP4430_CLKSEL_FCLK_SHIFT 24
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#define OMAP4430_CLKSEL_FCLK_WIDTH 0x2
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#define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT 25
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#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH 0x1
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#define OMAP4430_CLKSEL_L3_SHIFT 4
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#define OMAP4430_CLKSEL_L3_WIDTH 0x1
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#define OMAP4430_CLKSEL_L4_SHIFT 8
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#define OMAP4430_CLKSEL_L4_WIDTH 0x1
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#define OMAP4430_CLKSEL_OPP_SHIFT 0
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#define OMAP4430_CLKSEL_OPP_WIDTH 0x2
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#define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT 27
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#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH 0x3
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#define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK (0x7 << 24)
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#define OMAP4430_CLKSEL_SGX_FCLK_MASK (1 << 24)
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#define OMAP4430_CLKSEL_SOURCE_MASK (0x3 << 24)
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#define OMAP4430_CLKSEL_SOURCE_24_24_MASK (1 << 24)
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#define OMAP4430_CLKSEL_UTMI_P1_SHIFT 24
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#define OMAP4430_CLKSEL_UTMI_P1_WIDTH 0x1
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#define OMAP4430_CLKSEL_UTMI_P2_SHIFT 25
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#define OMAP4430_CLKSEL_UTMI_P2_WIDTH 0x1
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#define OMAP4430_CLKTRCTRL_SHIFT 0
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#define OMAP4430_CLKTRCTRL_MASK (0x3 << 0)
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#define OMAP4430_DPLL_BYP_CLKSEL_SHIFT 23
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#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH 0x1
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#define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK (0x1f << 0)
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#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT 8
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#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK (1 << 10)
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#define OMAP4430_DPLL_CLKOUT_DIV_SHIFT 0
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#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH 0x5
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#define OMAP4430_DPLL_CLKOUT_DIV_MASK (0x1f << 0)
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#define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK (0x7f << 0)
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#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK (1 << 8)
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#define OMAP4430_DPLL_DIV_MASK (0x7f << 0)
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#define OMAP4430_DPLL_DIV_0_7_MASK (0xff << 0)
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#define OMAP4430_DPLL_EN_MASK (0x7 << 0)
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#define OMAP4430_DPLL_LPMODE_EN_MASK (1 << 10)
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#define OMAP4430_DPLL_MULT_MASK (0x7ff << 8)
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#define OMAP4430_DPLL_MULT_USB_MASK (0xfff << 8)
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#define OMAP4430_DPLL_REGM4XEN_MASK (1 << 11)
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#define OMAP4430_DPLL_SD_DIV_MASK (0xff << 24)
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#define OMAP4430_DSS_STATDEP_SHIFT 8
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#define OMAP4430_DUCATI_STATDEP_SHIFT 0
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#define OMAP4430_GFX_STATDEP_SHIFT 10
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#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK (0x1f << 0)
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#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK (0x1f << 0)
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#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK (0x1f << 0)
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#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK (0x1f << 0)
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#define OMAP4430_IDLEST_SHIFT 16
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#define OMAP4430_IDLEST_MASK (0x3 << 16)
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#define OMAP4430_IVAHD_STATDEP_SHIFT 2
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#define OMAP4430_L3INIT_STATDEP_SHIFT 7
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#define OMAP4430_L3_1_STATDEP_SHIFT 5
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#define OMAP4430_L3_2_STATDEP_SHIFT 6
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#define OMAP4430_L4CFG_STATDEP_SHIFT 12
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#define OMAP4430_L4PER_STATDEP_SHIFT 13
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#define OMAP4430_L4SEC_STATDEP_SHIFT 14
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#define OMAP4430_L4WKUP_STATDEP_SHIFT 15
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#define OMAP4430_MEMIF_STATDEP_SHIFT 4
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#define OMAP4430_MODULEMODE_SHIFT 0
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#define OMAP4430_MODULEMODE_MASK (0x3 << 0)
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#define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT 9
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#define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT 8
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#define OMAP4430_OPTFCLKEN_CLK32K_SHIFT 8
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#define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT 8
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#define OMAP4430_OPTFCLKEN_DBCLK_SHIFT 8
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#define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT 8
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#define OMAP4430_OPTFCLKEN_FCLK_SHIFT 8
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#define OMAP4430_OPTFCLKEN_FCLK0_SHIFT 8
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#define OMAP4430_OPTFCLKEN_FCLK1_SHIFT 9
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#define OMAP4430_OPTFCLKEN_FCLK2_SHIFT 10
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#define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT 15
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#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT 13
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#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT 14
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#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT 11
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#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT 12
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#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT 8
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#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT 9
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#define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT 8
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#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT 10
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#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT 11
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#define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT 10
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#define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT 8
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#define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT 11
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#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT 8
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#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT 9
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#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT 10
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#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT 8
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#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT 9
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#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT 10
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#define OMAP4430_OPTFCLKEN_XCLK_SHIFT 8
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#define OMAP4430_PAD_CLKS_GATE_SHIFT 8
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#define OMAP4430_PMD_STM_MUX_CTRL_SHIFT 20
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#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH 0x2
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#define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT 22
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#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH 0x2
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#define OMAP4430_SCALE_FCLK_SHIFT 0
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#define OMAP4430_SCALE_FCLK_WIDTH 0x1
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#define OMAP4430_SLIMBUS_CLK_GATE_SHIFT 10
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#define OMAP4430_ST_DPLL_CLK_MASK (1 << 0)
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#define OMAP4430_SYS_CLKSEL_SHIFT 0
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#define OMAP4430_SYS_CLKSEL_WIDTH 0x3
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#define OMAP4430_TESLA_STATDEP_SHIFT 1
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#endif
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