// SPDX-License-Identifier: GPL-2.0-only
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/*
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* DSM-G600 board-level PCI initialization
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*
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* Copyright (C) 2006 Tower Technologies
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* Author: Alessandro Zummo <a.zummo@towertech.it>
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*
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* based on ixdp425-pci.c:
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* Copyright (C) 2002 Intel Corporation.
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* Copyright (C) 2003-2004 MontaVista Software, Inc.
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*
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* Maintainer: http://www.nslu2-linux.org/
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/mach/pci.h>
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#include <asm/mach-types.h>
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#include "irqs.h"
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#define MAX_DEV 4
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#define IRQ_LINES 3
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/* PCI controller GPIO to IRQ pin mappings */
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#define INTA 11
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#define INTB 10
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#define INTC 9
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#define INTD 8
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#define INTE 7
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#define INTF 6
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void __init dsmg600_pci_preinit(void)
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{
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
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irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
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ixp4xx_pci_preinit();
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}
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static int __init dsmg600_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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static int pci_irq_table[MAX_DEV][IRQ_LINES] = {
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{ IXP4XX_GPIO_IRQ(INTE), -1, -1 },
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{ IXP4XX_GPIO_IRQ(INTA), -1, -1 },
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{ IXP4XX_GPIO_IRQ(INTB), IXP4XX_GPIO_IRQ(INTC),
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IXP4XX_GPIO_IRQ(INTD) },
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{ IXP4XX_GPIO_IRQ(INTF), -1, -1 },
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};
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if (slot >= 1 && slot <= MAX_DEV && pin >= 1 && pin <= IRQ_LINES)
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return pci_irq_table[slot - 1][pin - 1];
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return -1;
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}
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struct hw_pci __initdata dsmg600_pci = {
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.nr_controllers = 1,
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.ops = &ixp4xx_ops,
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.preinit = dsmg600_pci_preinit,
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.setup = ixp4xx_setup,
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.map_irq = dsmg600_map_irq,
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};
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int __init dsmg600_pci_init(void)
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{
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if (machine_is_dsmg600())
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pci_common_init(&dsmg600_pci);
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return 0;
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}
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subsys_initcall(dsmg600_pci_init);
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