// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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* Copyright 2017-2018 NXP
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* Author: Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include "common.h"
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#define SMC_PMCTRL 0x10
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#define BP_PMCTRL_PSTOPO 16
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#define PSTOPO_PSTOP3 0x3
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#define PSTOPO_PSTOP2 0x2
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#define PSTOPO_PSTOP1 0x1
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#define BP_PMCTRL_RUNM 8
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#define RUNM_RUN 0
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#define BP_PMCTRL_STOPM 0
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#define STOPM_STOP 0
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#define BM_PMCTRL_PSTOPO (3 << BP_PMCTRL_PSTOPO)
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#define BM_PMCTRL_RUNM (3 << BP_PMCTRL_RUNM)
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#define BM_PMCTRL_STOPM (7 << BP_PMCTRL_STOPM)
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static void __iomem *smc1_base;
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int imx7ulp_set_lpm(enum ulp_cpu_pwr_mode mode)
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{
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u32 val = readl_relaxed(smc1_base + SMC_PMCTRL);
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/* clear all */
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val &= ~(BM_PMCTRL_RUNM | BM_PMCTRL_STOPM | BM_PMCTRL_PSTOPO);
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switch (mode) {
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case ULP_PM_RUN:
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/* system/bus clock enabled */
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val |= PSTOPO_PSTOP3 << BP_PMCTRL_PSTOPO;
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break;
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case ULP_PM_WAIT:
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/* system clock disabled, bus clock enabled */
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val |= PSTOPO_PSTOP2 << BP_PMCTRL_PSTOPO;
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break;
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case ULP_PM_STOP:
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/* system/bus clock disabled */
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val |= PSTOPO_PSTOP1 << BP_PMCTRL_PSTOPO;
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break;
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default:
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return -EINVAL;
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}
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writel_relaxed(val, smc1_base + SMC_PMCTRL);
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return 0;
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}
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void __init imx7ulp_pm_init(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx7ulp-smc1");
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smc1_base = of_iomap(np, 0);
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of_node_put(np);
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WARN_ON(!smc1_base);
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imx7ulp_set_lpm(ULP_PM_RUN);
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}
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