/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2011 Calxeda, Inc.
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*/
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#ifndef _MACH_HIGHBANK__SYSREGS_H_
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#define _MACH_HIGHBANK__SYSREGS_H_
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#include <linux/io.h>
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#include <linux/smp.h>
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#include <asm/smp_plat.h>
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#include <asm/smp_scu.h>
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#include "core.h"
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extern void __iomem *sregs_base;
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#define HB_SREG_A9_PWR_REQ 0xf00
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#define HB_SREG_A9_BOOT_STAT 0xf04
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#define HB_SREG_A9_BOOT_DATA 0xf08
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#define HB_PWR_SUSPEND 0
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#define HB_PWR_SOFT_RESET 1
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#define HB_PWR_HARD_RESET 2
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#define HB_PWR_SHUTDOWN 3
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#define SREG_CPU_PWR_CTRL(c) (0x200 + ((c) * 4))
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static inline void highbank_set_core_pwr(void)
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{
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int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
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if (scu_base_addr)
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scu_power_mode(scu_base_addr, SCU_PM_POWEROFF);
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else
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writel_relaxed(1, sregs_base + SREG_CPU_PWR_CTRL(cpu));
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}
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static inline void highbank_clear_core_pwr(void)
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{
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int cpu = MPIDR_AFFINITY_LEVEL(cpu_logical_map(smp_processor_id()), 0);
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if (scu_base_addr)
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scu_power_mode(scu_base_addr, SCU_PM_NORMAL);
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else
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writel_relaxed(0, sregs_base + SREG_CPU_PWR_CTRL(cpu));
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}
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static inline void highbank_set_pwr_suspend(void)
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{
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writel(HB_PWR_SUSPEND, sregs_base + HB_SREG_A9_PWR_REQ);
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highbank_set_core_pwr();
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}
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static inline void highbank_set_pwr_shutdown(void)
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{
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writel(HB_PWR_SHUTDOWN, sregs_base + HB_SREG_A9_PWR_REQ);
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highbank_set_core_pwr();
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}
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static inline void highbank_set_pwr_soft_reset(void)
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{
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writel(HB_PWR_SOFT_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
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highbank_set_core_pwr();
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}
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static inline void highbank_set_pwr_hard_reset(void)
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{
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writel(HB_PWR_HARD_RESET, sregs_base + HB_SREG_A9_PWR_REQ);
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highbank_set_core_pwr();
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}
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static inline void highbank_clear_pwr_request(void)
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{
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writel(~0UL, sregs_base + HB_SREG_A9_PWR_REQ);
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highbank_clear_core_pwr();
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}
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#endif
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