/*
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* AURORA shared L2 cache controller support
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*
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* Copyright (C) 2012 Marvell
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*
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* Yehuda Yitschak <yehuday@marvell.com>
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* Gregory CLEMENT <gregory.clement@free-electrons.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARM_HARDWARE_AURORA_L2_H
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#define __ASM_ARM_HARDWARE_AURORA_L2_H
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#define AURORA_SYNC_REG 0x700
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#define AURORA_RANGE_BASE_ADDR_REG 0x720
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#define AURORA_FLUSH_PHY_ADDR_REG 0x7f0
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#define AURORA_INVAL_RANGE_REG 0x774
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#define AURORA_CLEAN_RANGE_REG 0x7b4
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#define AURORA_FLUSH_RANGE_REG 0x7f4
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#define AURORA_ACR_REPLACEMENT_OFFSET 27
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#define AURORA_ACR_REPLACEMENT_MASK \
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(0x3 << AURORA_ACR_REPLACEMENT_OFFSET)
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#define AURORA_ACR_REPLACEMENT_TYPE_WAYRR \
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(0 << AURORA_ACR_REPLACEMENT_OFFSET)
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#define AURORA_ACR_REPLACEMENT_TYPE_LFSR \
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(1 << AURORA_ACR_REPLACEMENT_OFFSET)
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#define AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU \
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(3 << AURORA_ACR_REPLACEMENT_OFFSET)
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#define AURORA_ACR_PARITY_EN (1 << 21)
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#define AURORA_ACR_ECC_EN (1 << 20)
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#define AURORA_ACR_FORCE_WRITE_POLICY_OFFSET 0
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#define AURORA_ACR_FORCE_WRITE_POLICY_MASK \
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(0x3 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
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#define AURORA_ACR_FORCE_WRITE_POLICY_DIS \
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(0 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
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#define AURORA_ACR_FORCE_WRITE_BACK_POLICY \
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(1 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
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#define AURORA_ACR_FORCE_WRITE_THRO_POLICY \
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(2 << AURORA_ACR_FORCE_WRITE_POLICY_OFFSET)
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#define AURORA_ERR_CNT_REG 0x600
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#define AURORA_ERR_ATTR_CAP_REG 0x608
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#define AURORA_ERR_ADDR_CAP_REG 0x60c
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#define AURORA_ERR_WAY_CAP_REG 0x610
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#define AURORA_ERR_INJECT_CTL_REG 0x614
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#define AURORA_ERR_INJECT_MASK_REG 0x618
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#define AURORA_ERR_CNT_CLR_OFFSET 31
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#define AURORA_ERR_CNT_CLR \
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(0x1 << AURORA_ERR_CNT_CLR_OFFSET)
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#define AURORA_ERR_CNT_UE_OFFSET 16
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#define AURORA_ERR_CNT_UE_MASK \
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(0x7fff << AURORA_ERR_CNT_UE_OFFSET)
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#define AURORA_ERR_CNT_CE_OFFSET 0
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#define AURORA_ERR_CNT_CE_MASK \
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(0xffff << AURORA_ERR_CNT_CE_OFFSET)
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#define AURORA_ERR_ATTR_SRC_OFF 16
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#define AURORA_ERR_ATTR_SRC_MSK \
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(0x7 << AURORA_ERR_ATTR_SRC_OFF)
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#define AURORA_ERR_ATTR_TXN_OFF 12
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#define AURORA_ERR_ATTR_TXN_MSK \
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(0xf << AURORA_ERR_ATTR_TXN_OFF)
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#define AURORA_ERR_ATTR_ERR_OFF 8
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#define AURORA_ERR_ATTR_ERR_MSK \
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(0x3 << AURORA_ERR_ATTR_ERR_OFF)
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#define AURORA_ERR_ATTR_CAP_VALID_OFF 0
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#define AURORA_ERR_ATTR_CAP_VALID \
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(0x1 << AURORA_ERR_ATTR_CAP_VALID_OFF)
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#define AURORA_ERR_ADDR_CAP_ADDR_MASK 0xffffffe0
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#define AURORA_ERR_WAY_IDX_OFF 8
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#define AURORA_ERR_WAY_IDX_MSK \
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(0xfff << AURORA_ERR_WAY_IDX_OFF)
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#define AURORA_ERR_WAY_CAP_WAY_OFFSET 1
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#define AURORA_ERR_WAY_CAP_WAY_MASK \
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(0xf << AURORA_ERR_WAY_CAP_WAY_OFFSET)
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#define AURORA_ERR_INJECT_CTL_ADDR_MASK 0xfffffff0
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#define AURORA_ERR_ATTR_TXN_OFF 12
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#define AURORA_ERR_INJECT_CTL_EN_MASK 0x3
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#define AURORA_ERR_INJECT_CTL_EN_PARITY 0x2
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#define AURORA_ERR_INJECT_CTL_EN_ECC 0x1
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#define AURORA_MAX_RANGE_SIZE 1024
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#define AURORA_WAY_SIZE_SHIFT 2
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#define AURORA_CTRL_FW 0x100
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/* chose a number outside L2X0_CACHE_ID_PART_MASK to be sure to make
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* the distinction between a number coming from hardware and a number
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* coming from the device tree */
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#define AURORA_CACHE_ID 0x100
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#endif /* __ASM_ARM_HARDWARE_AURORA_L2_H */
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