1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
| // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
| /*
| * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
| */
|
| &cru {
| assigned-clocks =
| <&pmucru CLK_RTC32K>, <&pmucru PLL_GPLL>,
| <&pmucru PCLK_PDPMU>, <&cru PLL_CPLL>,
| <&cru PLL_HPLL>, <&cru ARMCLK>,
| <&cru ACLK_PDBUS>, <&cru HCLK_PDBUS>,
| <&cru PCLK_PDBUS>, <&cru ACLK_PDPHP>,
| <&cru HCLK_PDPHP>, <&cru HCLK_PDAUDIO>,
| <&cru HCLK_PDCORE_NIU>;
| assigned-clock-rates =
| <32768>, <1188000000>,
| <100000000>, <491520000>,
| <1400000000>, <600000000>,
| <500000000>, <200000000>,
| <100000000>, <300000000>,
| <200000000>, <150000000>,
| <200000000>;
| };
|
| &i2s0_8ch {
| clocks = <&cru MCLK_I2S0_TX>, <&cru MCLK_I2S0_RX>, <&cru HCLK_I2S0>,
| <&cru MCLK_I2S0_TX_DIV>, <&cru MCLK_I2S0_RX_DIV>,
| <&cru PLL_CPLL>, <&cru PLL_CPLL>;
| clock-names = "mclk_tx", "mclk_rx", "hclk",
| "mclk_tx_src", "mclk_rx_src",
| "mclk_root0", "mclk_root1";
| rockchip,mclk-calibrate;
| };
|
|
