/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#include <dt-bindings/clock/rockchip-ddr.h>
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#include <dt-bindings/dram/rockchip,rk322x.h>
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/ {
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dram_timing: dram_timing {
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compatible = "rockchip,dram-timing";
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dram_spd_bin = <DDR3_DEFAULT>;
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sr_idle = <0x18>;
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pd_idle = <0x20>;
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dram_dll_disb_freq = <300>;
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phy_dll_disb_freq = <400>;
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dram_odt_disb_freq = <333>;
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phy_odt_disb_freq = <333>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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lpddr3_drv = <LP3_DS_34ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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lpddr2_drv = <LP2_DS_34ohm>;
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/* lpddr2 not supported odt */
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phy_ddr3_clk_drv = <PHY_DDR3_RON_RTT_45ohm>;
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phy_ddr3_cmd_drv = <PHY_DDR3_RON_RTT_45ohm>;
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phy_ddr3_dqs_drv = <PHY_DDR3_RON_RTT_34ohm>;
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phy_ddr3_odt = <PHY_DDR3_RON_RTT_225ohm>;
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phy_lp23_clk_drv = <PHY_LP23_RON_RTT_43ohm>;
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phy_lp23_cmd_drv = <PHY_LP23_RON_RTT_34ohm>;
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phy_lp23_dqs_drv = <PHY_LP23_RON_RTT_34ohm>;
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phy_lp3_odt = <PHY_LP23_RON_RTT_240ohm>;
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};
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};
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