// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device Tree Source for OMAP34XX/OMAP36XX clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*/
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&cm_clocks {
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security_l4_ick2: security_l4_ick2 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&l4_ick>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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aes1_ick: aes1_ick@a14 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&security_l4_ick2>;
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ti,bit-shift = <3>;
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reg = <0x0a14>;
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};
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rng_ick: rng_ick@a14 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&security_l4_ick2>;
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reg = <0x0a14>;
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ti,bit-shift = <2>;
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};
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sha11_ick: sha11_ick@a14 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&security_l4_ick2>;
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reg = <0x0a14>;
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ti,bit-shift = <1>;
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};
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des1_ick: des1_ick@a14 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&security_l4_ick2>;
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reg = <0x0a14>;
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ti,bit-shift = <0>;
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};
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cam_mclk: cam_mclk@f00 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&dpll4_m5x2_ck>;
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ti,bit-shift = <0>;
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reg = <0x0f00>;
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ti,set-rate-parent;
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};
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cam_ick: cam_ick@f10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-no-wait-interface-clock";
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clocks = <&l4_ick>;
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reg = <0x0f10>;
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ti,bit-shift = <0>;
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};
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csi2_96m_fck: csi2_96m_fck@f00 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&core_96m_fck>;
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reg = <0x0f00>;
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ti,bit-shift = <1>;
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};
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security_l3_ick: security_l3_ick {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&l3_ick>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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pka_ick: pka_ick@a14 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&security_l3_ick>;
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reg = <0x0a14>;
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ti,bit-shift = <4>;
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};
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icr_ick: icr_ick@a10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <29>;
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};
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des2_ick: des2_ick@a10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <26>;
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};
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mspro_ick: mspro_ick@a10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <23>;
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};
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mailboxes_ick: mailboxes_ick@a10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l4_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <7>;
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};
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ssi_l4_ick: ssi_l4_ick {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&l4_ick>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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sr1_fck: sr1_fck@c00 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&sys_ck>;
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reg = <0x0c00>;
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ti,bit-shift = <6>;
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};
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sr2_fck: sr2_fck@c00 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&sys_ck>;
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reg = <0x0c00>;
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ti,bit-shift = <7>;
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};
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sr_l4_ick: sr_l4_ick {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&l4_ick>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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dpll2_fck: dpll2_fck@40 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <19>;
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ti,max-div = <7>;
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reg = <0x0040>;
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ti,index-starts-at-one;
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};
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dpll2_ck: dpll2_ck@4 {
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#clock-cells = <0>;
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compatible = "ti,omap3-dpll-clock";
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clocks = <&sys_ck>, <&dpll2_fck>;
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reg = <0x0004>, <0x0024>, <0x0040>, <0x0034>;
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ti,low-power-stop;
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ti,lock;
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ti,low-power-bypass;
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};
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dpll2_m2_ck: dpll2_m2_ck@44 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll2_ck>;
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ti,max-div = <31>;
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reg = <0x0044>;
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ti,index-starts-at-one;
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};
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iva2_ck: iva2_ck@0 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&dpll2_m2_ck>;
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reg = <0x0000>;
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ti,bit-shift = <0>;
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};
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modem_fck: modem_fck@a00 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&sys_ck>;
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reg = <0x0a00>;
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ti,bit-shift = <31>;
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};
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sad2d_ick: sad2d_ick@a10 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l3_ick>;
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reg = <0x0a10>;
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ti,bit-shift = <3>;
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};
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mad2d_ick: mad2d_ick@a18 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l3_ick>;
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reg = <0x0a18>;
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ti,bit-shift = <3>;
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};
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mspro_fck: mspro_fck@a00 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&core_96m_fck>;
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reg = <0x0a00>;
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ti,bit-shift = <23>;
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};
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};
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&cm_clockdomains {
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cam_clkdm: cam_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&cam_ick>, <&csi2_96m_fck>;
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};
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iva2_clkdm: iva2_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&iva2_ck>;
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};
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dpll2_clkdm: dpll2_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dpll2_ck>;
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};
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wkup_clkdm: wkup_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&gpio1_dbck>, <&wdt2_fck>, <&wdt2_ick>, <&wdt1_ick>,
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<&gpio1_ick>, <&omap_32ksync_ick>, <&gpt12_ick>,
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<&gpt1_ick>, <&sr1_fck>, <&sr2_fck>;
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};
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d2d_clkdm: d2d_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&modem_fck>, <&sad2d_ick>, <&mad2d_ick>;
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};
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core_l4_clkdm: core_l4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
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<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
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<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
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<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
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<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
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<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
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<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
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<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
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<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>, <&icr_ick>,
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<&des2_ick>, <&mspro_ick>, <&mailboxes_ick>,
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<&rng_ick>, <&mspro_fck>;
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};
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};
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