// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Device Tree Source for OMAP2420 clock data
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*
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* Copyright (C) 2014 Texas Instruments, Inc.
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*/
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&prcm_clocks {
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sys_clkout2_src_gate: sys_clkout2_src_gate@70 {
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#clock-cells = <0>;
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compatible = "ti,composite-no-wait-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <15>;
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reg = <0x0070>;
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};
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sys_clkout2_src_mux: sys_clkout2_src_mux@70 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
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ti,bit-shift = <8>;
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reg = <0x0070>;
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};
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sys_clkout2_src: sys_clkout2_src {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&sys_clkout2_src_gate>, <&sys_clkout2_src_mux>;
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};
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sys_clkout2: sys_clkout2@70 {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&sys_clkout2_src>;
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ti,bit-shift = <11>;
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ti,max-div = <64>;
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reg = <0x0070>;
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ti,index-power-of-two;
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};
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dsp_gate_ick: dsp_gate_ick@810 {
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#clock-cells = <0>;
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compatible = "ti,composite-interface-clock";
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clocks = <&dsp_fck>;
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ti,bit-shift = <1>;
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reg = <0x0810>;
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};
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dsp_div_ick: dsp_div_ick@840 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&dsp_fck>;
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ti,bit-shift = <5>;
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ti,max-div = <3>;
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reg = <0x0840>;
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ti,index-starts-at-one;
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};
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dsp_ick: dsp_ick {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&dsp_gate_ick>, <&dsp_div_ick>;
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};
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iva1_gate_ifck: iva1_gate_ifck@800 {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <10>;
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reg = <0x0800>;
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};
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iva1_div_ifck: iva1_div_ifck@840 {
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#clock-cells = <0>;
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compatible = "ti,composite-divider-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <8>;
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reg = <0x0840>;
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
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};
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iva1_ifck: iva1_ifck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&iva1_gate_ifck>, <&iva1_div_ifck>;
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};
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iva1_ifck_div: iva1_ifck_div {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&iva1_ifck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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iva1_mpu_int_ifck: iva1_mpu_int_ifck@800 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&iva1_ifck_div>;
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ti,bit-shift = <8>;
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reg = <0x0800>;
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};
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wdt3_ick: wdt3_ick@210 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <28>;
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reg = <0x0210>;
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};
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wdt3_fck: wdt3_fck@200 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_32k_ck>;
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ti,bit-shift = <28>;
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reg = <0x0200>;
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};
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mmc_ick: mmc_ick@210 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <26>;
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reg = <0x0210>;
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};
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mmc_fck: mmc_fck@200 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_96m_ck>;
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ti,bit-shift = <26>;
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reg = <0x0200>;
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};
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eac_ick: eac_ick@210 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&l4_ck>;
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ti,bit-shift = <24>;
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reg = <0x0210>;
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};
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eac_fck: eac_fck@200 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_96m_ck>;
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ti,bit-shift = <24>;
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reg = <0x0200>;
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};
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i2c1_fck: i2c1_fck@200 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_12m_ck>;
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ti,bit-shift = <19>;
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reg = <0x0200>;
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};
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i2c2_fck: i2c2_fck@200 {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&func_12m_ck>;
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ti,bit-shift = <20>;
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reg = <0x0200>;
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};
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vlynq_ick: vlynq_ick@210 {
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#clock-cells = <0>;
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compatible = "ti,omap3-interface-clock";
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clocks = <&core_l3_ck>;
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ti,bit-shift = <3>;
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reg = <0x0210>;
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};
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vlynq_gate_fck: vlynq_gate_fck@200 {
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#clock-cells = <0>;
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compatible = "ti,composite-gate-clock";
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clocks = <&core_ck>;
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ti,bit-shift = <3>;
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reg = <0x0200>;
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};
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core_d18_ck: core_d18_ck {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&core_ck>;
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clock-mult = <1>;
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clock-div = <18>;
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};
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vlynq_mux_fck: vlynq_mux_fck@240 {
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#clock-cells = <0>;
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compatible = "ti,composite-mux-clock";
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clocks = <&func_96m_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&dummy_ck>, <&core_d6_ck>, <&dummy_ck>, <&core_d8_ck>, <&core_d9_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d12_ck>, <&dummy_ck>, <&dummy_ck>, <&dummy_ck>, <&core_d16_ck>, <&dummy_ck>, <&core_d18_ck>;
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ti,bit-shift = <15>;
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reg = <0x0240>;
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};
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vlynq_fck: vlynq_fck {
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#clock-cells = <0>;
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compatible = "ti,composite-clock";
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clocks = <&vlynq_gate_fck>, <&vlynq_mux_fck>;
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};
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};
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&prcm_clockdomains {
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gfx_clkdm: gfx_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&gfx_ick>;
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};
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core_l3_clkdm: core_l3_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&cam_fck>, <&vlynq_ick>, <&usb_fck>;
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};
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wkup_clkdm: wkup_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dpll_ck>, <&emul_ck>, <&gpt1_ick>, <&gpios_ick>,
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<&gpios_fck>, <&mpu_wdt_ick>, <&mpu_wdt_fck>,
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<&sync_32k_ick>, <&wdt1_ick>, <&omapctrl_ick>;
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};
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iva1_clkdm: iva1_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&iva1_mpu_int_ifck>;
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};
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dss_clkdm: dss_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&dss_ick>, <&dss_54m_fck>;
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};
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core_l4_clkdm: core_l4_clkdm {
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compatible = "ti,clockdomain";
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clocks = <&ssi_l4_ick>, <&gpt2_ick>, <&gpt3_ick>, <&gpt4_ick>,
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<&gpt5_ick>, <&gpt6_ick>, <&gpt7_ick>, <&gpt8_ick>,
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<&gpt9_ick>, <&gpt10_ick>, <&gpt11_ick>, <&gpt12_ick>,
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<&mcbsp1_ick>, <&mcbsp2_ick>, <&mcspi1_ick>,
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<&mcspi1_fck>, <&mcspi2_ick>, <&mcspi2_fck>,
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<&uart1_ick>, <&uart1_fck>, <&uart2_ick>, <&uart2_fck>,
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<&uart3_ick>, <&uart3_fck>, <&cam_ick>,
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<&mailboxes_ick>, <&wdt4_ick>, <&wdt4_fck>,
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<&wdt3_ick>, <&wdt3_fck>, <&mspro_ick>, <&mspro_fck>,
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<&mmc_ick>, <&mmc_fck>, <&fac_ick>, <&fac_fck>,
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<&eac_ick>, <&eac_fck>, <&hdq_ick>, <&hdq_fck>,
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<&i2c1_ick>, <&i2c1_fck>, <&i2c2_ick>, <&i2c2_fck>,
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<&des_ick>, <&sha_ick>, <&rng_ick>, <&aes_ick>,
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<&pka_ick>;
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};
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};
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&func_96m_ck {
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compatible = "fixed-factor-clock";
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clocks = <&apll96_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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&dsp_div_fck {
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>, <0>, <0>, <0>, <12>;
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};
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&ssi_ssr_sst_div_fck {
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ti,dividers = <0>, <1>, <2>, <3>, <4>, <0>, <6>, <0>, <8>;
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};
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