// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 2015 Phytec Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*/
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/ {
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model = "Phytec AM335x phyBOARD-WEGA";
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compatible = "phytec,am335x-wega", "phytec,am335x-phycore-som", "ti,am33xx";
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sound: sound_iface {
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compatible = "ti,da830-evm-audio";
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};
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vcc3v3: fixedregulator1 {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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};
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/* Audio */
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&am33xx_pinmux {
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mcasp0_pins: pinmux_mcasp0 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
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>;
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};
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};
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&i2c0 {
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tlv320aic3007: tlv320aic3007@18 {
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compatible = "ti,tlv320aic3007";
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reg = <0x18>;
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AVDD-supply = <&vcc3v3>;
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IOVDD-supply = <&vcc3v3>;
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DRVDD-supply = <&vcc3v3>;
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DVDD-supply = <&vdig1_reg>;
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status = "okay";
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};
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};
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&mcasp0 {
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pinctrl-names = "default";
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pinctrl-0 = <&mcasp0_pins>;
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op-mode = <0>; /* DAVINCI_MCASP_IIS_MODE */
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tdm-slots = <2>;
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serial-dir = <
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2 1 0 0 /* # 0: INACTIVE, 1: TX, 2: RX */
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>;
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tx-num-evt = <16>;
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rt-num-evt = <16>;
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status = "okay";
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};
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&sound {
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ti,model = "AM335x-Wega";
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ti,audio-codec = <&tlv320aic3007>;
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ti,mcasp-controller = <&mcasp0>;
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ti,audio-routing =
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"Line Out", "LLOUT",
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"Line Out", "RLOUT",
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"LINE1L", "Line In",
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"LINE1R", "Line In";
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clocks = <&mcasp0_fck>;
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clock-names = "mclk";
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status = "okay";
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};
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/* CAN Busses */
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&am33xx_pinmux {
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dcan1_pins: pinmux_dcan1 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
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AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
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>;
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};
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};
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&dcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&dcan1_pins>;
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status = "okay";
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};
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/* Ethernet */
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&am33xx_pinmux {
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ethernet1_pins: pinmux_ethernet1 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
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AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */
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>;
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};
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};
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&cpsw_emac1 {
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phy-handle = <&phy1>;
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phy-mode = "mii";
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dual_emac_res_vlan = <2>;
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};
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&davinci_mdio {
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&mac {
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slaves = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <ðernet0_pins ðernet1_pins>;
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dual_emac = <1>;
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};
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/* MMC */
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&am33xx_pinmux {
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mmc1_pins: pinmux_mmc1 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
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>;
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};
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};
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&mmc1 {
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vmmc-supply = <&vcc3v3>;
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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/* Power */
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&vdig1_reg {
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regulator-boot-on;
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regulator-always-on;
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};
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/* UARTs */
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&am33xx_pinmux {
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uart0_pins: pinmux_uart0 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
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>;
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};
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uart1_pins: pinmux_uart1_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_pins>;
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status = "okay";
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};
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&usb1 {
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dr_mode = "host";
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};
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