// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2019 Phytec Messtechnik GmbH
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* Author: Teresa Remmet <t.remmet@phytec.de>
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*
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*/
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/ {
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model = "Phytec AM335x phyBOARD-REGOR";
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compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx";
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vcc3v3: fixedregulator@1 {
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compatible = "regulator-fixed";
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regulator-name = "vcc3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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};
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/* User IO */
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user_leds: user_leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&user_leds_pins>;
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run_stop-led {
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gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "gpio";
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default-state = "off";
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};
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error-led {
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gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "gpio";
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default-state = "off";
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};
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};
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};
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/* User Leds */
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&am33xx_pinmux {
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user_leds_pins: pinmux_user_leds {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* lcd_hsync.gpio2_22 */
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AM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7) /* mcasp0_fsx.gpio3_15 */
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>;
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};
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};
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/* CAN Busses */
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&am33xx_pinmux {
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dcan1_pins: pinmux_dcan1 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */
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AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */
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>;
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};
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};
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&dcan1 {
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pinctrl-names = "default";
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pinctrl-0 = <&dcan1_pins>;
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status = "okay";
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};
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/* Ethernet */
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&am33xx_pinmux {
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ethernet1_pins: pinmux_ethernet1 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1) /* gpmc_a0.mii2_txen */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a1.mii2_rxdv */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1) /* gpmc_a2.mii2_txd3 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1) /* gpmc_a3.mii2_txd2 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1) /* gpmc_a4.mii2_txd1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1) /* gpmc_a5.mii2_txd0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a6.mii2_txclk */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a7.mii2_rxclk */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a8.mii2_rxd3 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a9.mii2_rxd2 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a10.mii2_rxd1 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_a11.mii2_rxd0 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_wpn.mii2_rxerr */
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AM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1) /* gpmc_ben1.mii2_col */
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>;
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};
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};
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&cpsw_emac1 {
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phy-handle = <&phy1>;
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phy-mode = "mii";
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dual_emac_res_vlan = <2>;
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};
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&davinci_mdio {
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phy1: ethernet-phy@1 {
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reg = <1>;
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};
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};
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&mac {
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slaves = <2>;
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pinctrl-names = "default";
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pinctrl-0 = <ðernet0_pins ðernet1_pins>;
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dual_emac = <1>;
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};
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/* GPIOs */
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&am33xx_pinmux {
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pinctrl-names = "default";
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pinctrl-0 = <&user_gpios_pins>;
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user_gpios_pins: pinmux_user_gpios {
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pinctrl-single,pins = <
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/* DIGIN 1-4 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7) /* gpmc_ad11.gpio0_27 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7) /* gpmc_ad10.gpio0_26 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7) /* gpmc_ad9.gpio0_23 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7) /* gpmc_ad8.gpio0_22 */
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/* DIGOUT 1-4 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad15.gpio1_15 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad14.gpio1_14 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad13.gpio1_13 */
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AM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7) /* gpmc_ad12.gpio1_12 */
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>;
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};
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};
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/* MMC */
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&am33xx_pinmux {
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mmc1_pins: pinmux_mmc1 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7) /* spi0_cs1.mmc0_sdcd */
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>;
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};
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};
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&mmc1 {
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vmmc-supply = <&vcc3v3>;
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bus-width = <4>;
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pinctrl-names = "default";
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pinctrl-0 = <&mmc1_pins>;
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cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
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status = "okay";
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};
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/* RTC */
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&i2c_rtc {
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status = "okay";
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};
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/* UARTs */
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&am33xx_pinmux {
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uart0_pins: pinmux_uart0 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
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>;
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};
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uart2_pins: pinmux_uart2 {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1) /* mii1_tx_clk.uart2_rxd */
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AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1) /* mii1_rx_clk.uart2_txd */
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>;
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};
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};
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&uart0 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins>;
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status = "okay";
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};
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&uart2 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart2_pins>;
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status = "okay";
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};
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/* RS485 - UART1 */
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&am33xx_pinmux {
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uart1_rs485_pins: pinmux_uart1_rs485_pins {
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pinctrl-single,pins = <
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AM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
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AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0)
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>;
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};
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};
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&uart1 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart1_rs485_pins>;
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status = "okay";
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linux,rs485-enabled-at-boot-time;
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};
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