/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef __ASM_ALPHA_FPU_H
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#define __ASM_ALPHA_FPU_H
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#include <asm/special_insns.h>
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#include <uapi/asm/fpu.h>
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/* The following two functions don't need trapb/excb instructions
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around the mf_fpcr/mt_fpcr instructions because (a) the kernel
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never generates arithmetic faults and (b) call_pal instructions
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are implied trap barriers. */
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static inline unsigned long
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rdfpcr(void)
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{
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unsigned long tmp, ret;
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#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
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__asm__ __volatile__ (
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"ftoit $f0,%0\n\t"
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"mf_fpcr $f0\n\t"
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"ftoit $f0,%1\n\t"
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"itoft %0,$f0"
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: "=r"(tmp), "=r"(ret));
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#else
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__asm__ __volatile__ (
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"stt $f0,%0\n\t"
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"mf_fpcr $f0\n\t"
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"stt $f0,%1\n\t"
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"ldt $f0,%0"
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: "=m"(tmp), "=m"(ret));
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#endif
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return ret;
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}
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static inline void
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wrfpcr(unsigned long val)
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{
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unsigned long tmp;
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#if defined(CONFIG_ALPHA_EV6) || defined(CONFIG_ALPHA_EV67)
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__asm__ __volatile__ (
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"ftoit $f0,%0\n\t"
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"itoft %1,$f0\n\t"
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"mt_fpcr $f0\n\t"
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"itoft %0,$f0"
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: "=&r"(tmp) : "r"(val));
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#else
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__asm__ __volatile__ (
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"stt $f0,%0\n\t"
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"ldt $f0,%1\n\t"
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"mt_fpcr $f0\n\t"
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"ldt $f0,%0"
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: "=m"(tmp) : "m"(val));
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#endif
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}
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static inline unsigned long
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swcr_update_status(unsigned long swcr, unsigned long fpcr)
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{
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/* EV6 implements most of the bits in hardware. Collect
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the acrued exception bits from the real fpcr. */
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if (implver() == IMPLVER_EV6) {
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swcr &= ~IEEE_STATUS_MASK;
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swcr |= (fpcr >> 35) & IEEE_STATUS_MASK;
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}
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return swcr;
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}
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extern unsigned long alpha_read_fp_reg (unsigned long reg);
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extern void alpha_write_fp_reg (unsigned long reg, unsigned long val);
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extern unsigned long alpha_read_fp_reg_s (unsigned long reg);
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extern void alpha_write_fp_reg_s (unsigned long reg, unsigned long val);
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#endif /* __ASM_ALPHA_FPU_H */
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