/*
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* Copyright 2020 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define MODULE_TAG "vpu_api_mlvec"
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#include <fcntl.h>
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#include "string.h"
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#include "mpp_mem.h"
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#include "mpp_debug.h"
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#include "mpp_common.h"
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#include "vpu_api_mlvec.h"
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#include "vpu_api_legacy.h"
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#define VPU_API_DBG_MLVEC_FUNC (0x00010000)
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#define VPU_API_DBG_MLVEC_FLOW (0x00020000)
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#define mlvec_dbg_func(fmt, ...) vpu_api_dbg_f(VPU_API_DBG_MLVEC_FUNC, fmt, ## __VA_ARGS__)
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#define mlvec_dbg_flow(fmt, ...) vpu_api_dbg_f(VPU_API_DBG_MLVEC_FLOW, fmt, ## __VA_ARGS__)
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typedef struct VpuApiMlvecImpl_t {
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MppCtx mpp;
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MppApi *mpi;
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MppEncCfg enc_cfg;
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VpuApiMlvecStaticCfg st_cfg;
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VpuApiMlvecDynamicCfg dy_cfg;
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} VpuApiMlvecImpl;
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MPP_RET vpu_api_mlvec_init(VpuApiMlvec *ctx)
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{
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if (NULL == ctx) {
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mpp_err_f("invalid NULL input\n");
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return MPP_ERR_NULL_PTR;
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}
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mlvec_dbg_func("enter %p\n", ctx);
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VpuApiMlvecImpl *impl = mpp_calloc(VpuApiMlvecImpl, 1);
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if (NULL == impl)
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mpp_err_f("failed to create MLVEC context\n");
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mpp_assert(sizeof(VpuApiMlvecStaticCfg) == sizeof(EncParameter_t));
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/* default disable frame_qp setup */
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impl->dy_cfg.frame_qp = -1;
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*ctx = impl;
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mlvec_dbg_func("leave %p %p\n", ctx, impl);
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return (impl) ? (MPP_OK) : (MPP_NOK);
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}
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MPP_RET vpu_api_mlvec_deinit(VpuApiMlvec ctx)
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{
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mlvec_dbg_func("enter %p\n", ctx);
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MPP_FREE(ctx);
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mlvec_dbg_func("leave %p\n", ctx);
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return MPP_OK;
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}
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MPP_RET vpu_api_mlvec_setup(VpuApiMlvec ctx, MppCtx mpp, MppApi *mpi, MppEncCfg enc_cfg)
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{
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if (NULL == ctx || NULL == mpp || NULL == mpi || NULL == enc_cfg) {
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mpp_err_f("invalid NULL input ctx %p mpp %p mpi %p cfg %p\n",
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ctx, mpp, mpi, enc_cfg);
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return MPP_ERR_NULL_PTR;
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}
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mlvec_dbg_func("enter %p\n", ctx);
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VpuApiMlvecImpl *impl = (VpuApiMlvecImpl *)ctx;
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impl->mpp = mpp;
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impl->mpi = mpi;
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impl->enc_cfg = enc_cfg;
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mlvec_dbg_func("leave %p\n", ctx);
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return MPP_OK;
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}
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MPP_RET vpu_api_mlvec_check_cfg(void *p)
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{
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if (NULL == p) {
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mpp_err_f("invalid NULL input\n");
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return MPP_ERR_NULL_PTR;
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}
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VpuApiMlvecStaticCfg *cfg = (VpuApiMlvecStaticCfg *)p;
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RK_U32 magic = cfg->magic;
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MPP_RET ret = MPP_OK;
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if ((((magic >> 24) & 0xff) != MLVEC_MAGIC) ||
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(((magic >> 16) & 0xff) != MLVEC_VERSION))
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ret = MPP_NOK;
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mlvec_dbg_flow("check mlvec cfg magic %08x %s\n", magic,
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(ret == MPP_OK) ? "success" : "failed");
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return ret;
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}
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MPP_RET vpu_api_mlvec_set_st_cfg(VpuApiMlvec ctx, VpuApiMlvecStaticCfg *cfg)
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{
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if (NULL == ctx || NULL == cfg) {
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mpp_err_f("invalid NULL input ctx %p cfg %p\n");
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return MPP_ERR_NULL_PTR;
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}
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mlvec_dbg_func("enter ctx %p cfg %p\n", ctx, cfg);
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/* check mlvec magic word */
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if (vpu_api_mlvec_check_cfg(cfg))
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return MPP_NOK;
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MPP_RET ret = MPP_OK;
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/* update static configure */
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VpuApiMlvecImpl *impl = (VpuApiMlvecImpl *)ctx;
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memcpy(&impl->st_cfg, cfg, sizeof(impl->st_cfg));
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cfg = &impl->st_cfg;
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/* get mpp context and check */
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MppCtx mpp_ctx = impl->mpp;
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MppApi *mpi = impl->mpi;
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MppEncCfg enc_cfg = impl->enc_cfg;
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mpp_assert(mpp_ctx);
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mpp_assert(mpi);
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mpp_assert(enc_cfg);
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/* start control mpp */
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mlvec_dbg_flow("hdr_on_idr %d\n", cfg->hdr_on_idr);
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MppEncHeaderMode mode = cfg->hdr_on_idr ?
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MPP_ENC_HEADER_MODE_EACH_IDR :
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MPP_ENC_HEADER_MODE_DEFAULT;
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ret = mpi->control(mpp_ctx, MPP_ENC_SET_HEADER_MODE, &mode);
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if (ret)
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mpp_err("setup enc header mode %d failed ret %d\n", mode, ret);
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mlvec_dbg_flow("add_prefix %d\n", cfg->add_prefix);
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mpp_enc_cfg_set_s32(enc_cfg, "h264:prefix_mode", cfg->add_prefix);
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mlvec_dbg_flow("slice_mbs %d\n", cfg->slice_mbs);
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if (cfg->slice_mbs) {
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mpp_enc_cfg_set_u32(enc_cfg, "split:mode", MPP_ENC_SPLIT_BY_CTU);
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mpp_enc_cfg_set_u32(enc_cfg, "split:arg", cfg->slice_mbs);
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} else
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mpp_enc_cfg_set_u32(enc_cfg, "split:mode", MPP_ENC_SPLIT_NONE);
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/* NOTE: ltr_frames is already configured */
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vpu_api_mlvec_set_dy_max_tid(ctx, cfg->max_tid);
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mlvec_dbg_func("leave ctx %p ret %d\n", ctx, ret);
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return ret;
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}
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MPP_RET vpu_api_mlvec_set_dy_cfg(VpuApiMlvec ctx, VpuApiMlvecDynamicCfg *cfg, MppMeta meta)
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{
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if (NULL == ctx || NULL == cfg || NULL == meta) {
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mpp_err_f("invalid NULL input ctx %p cfg %p meta %p\n",
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ctx, cfg, meta);
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return MPP_ERR_NULL_PTR;
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}
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mlvec_dbg_func("enter ctx %p cfg %p meta %p\n", ctx, cfg, meta);
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MPP_RET ret = MPP_OK;
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VpuApiMlvecImpl *impl = (VpuApiMlvecImpl *)ctx;
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VpuApiMlvecDynamicCfg *dst = &impl->dy_cfg;
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/* clear non-sticky flag first */
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dst->mark_ltr = -1;
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dst->use_ltr = -1;
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/* frame qp and base layer pid is sticky flag */
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/* update flags */
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if (cfg->updated) {
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if (cfg->updated & VPU_API_ENC_MARK_LTR_UPDATED)
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dst->mark_ltr = cfg->mark_ltr;
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if (cfg->updated & VPU_API_ENC_USE_LTR_UPDATED)
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dst->use_ltr = cfg->use_ltr;
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if (cfg->updated & VPU_API_ENC_FRAME_QP_UPDATED)
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dst->frame_qp = cfg->frame_qp;
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if (cfg->updated & VPU_API_ENC_BASE_PID_UPDATED)
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dst->base_layer_pid = cfg->base_layer_pid;
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/* dynamic max temporal layer count updated go through mpp ref cfg */
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cfg->updated = 0;
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}
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mlvec_dbg_flow("ltr mark %2d use %2d frm qp %2d blpid %d\n", dst->mark_ltr,
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dst->use_ltr, dst->frame_qp, dst->base_layer_pid);
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/* setup next frame configure */
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if (dst->mark_ltr >= 0)
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mpp_meta_set_s32(meta, KEY_ENC_MARK_LTR, dst->mark_ltr);
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if (dst->use_ltr >= 0)
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mpp_meta_set_s32(meta, KEY_ENC_USE_LTR, dst->use_ltr);
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if (dst->frame_qp >= 0)
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mpp_meta_set_s32(meta, KEY_ENC_FRAME_QP, dst->frame_qp);
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if (dst->base_layer_pid >= 0)
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mpp_meta_set_s32(meta, KEY_ENC_BASE_LAYER_PID, dst->base_layer_pid);
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mlvec_dbg_func("leave ctx %p ret %d\n", ctx, ret);
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return ret;
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}
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MPP_RET vpu_api_mlvec_set_dy_max_tid(VpuApiMlvec ctx, RK_S32 max_tid)
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{
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if (NULL == ctx) {
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mpp_err_f("invalid NULL input\n");
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return MPP_ERR_NULL_PTR;
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}
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mlvec_dbg_func("enter ctx %p max_tid %d\n", ctx, max_tid);
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MPP_RET ret = MPP_OK;
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VpuApiMlvecImpl *impl = (VpuApiMlvecImpl *)ctx;
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MppCtx mpp_ctx = impl->mpp;
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MppApi *mpi = impl->mpi;
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MppEncCfg enc_cfg = impl->enc_cfg;
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mpp_assert(mpp_ctx);
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mpp_assert(mpi);
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mpp_assert(enc_cfg);
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MppEncRefLtFrmCfg lt_ref[16];
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MppEncRefStFrmCfg st_ref[16];
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RK_S32 lt_cfg_cnt = 0;
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RK_S32 st_cfg_cnt = 0;
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RK_S32 tid0_loop = 0;
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RK_S32 ltr_frames = impl->st_cfg.ltr_frames;
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memset(lt_ref, 0, sizeof(lt_ref));
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memset(st_ref, 0, sizeof(st_ref));
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mlvec_dbg_flow("ltr_frames %d\n", ltr_frames);
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mlvec_dbg_flow("max_tid %d\n", max_tid);
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switch (max_tid) {
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case 0 : {
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st_ref[0].is_non_ref = 0;
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st_ref[0].temporal_id = 0;
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st_ref[0].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[0].ref_arg = 0;
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st_ref[0].repeat = 0;
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st_cfg_cnt = 1;
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tid0_loop = 1;
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mlvec_dbg_flow("no tsvc\n");
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} break;
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case 1 : {
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/* set tsvc2 st-ref struct */
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/* st 0 layer 0 - ref */
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st_ref[0].is_non_ref = 0;
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st_ref[0].temporal_id = 0;
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st_ref[0].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[0].ref_arg = 0;
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st_ref[0].repeat = 0;
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/* st 1 layer 1 - non-ref */
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st_ref[1].is_non_ref = 1;
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st_ref[1].temporal_id = 1;
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st_ref[1].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[1].ref_arg = 0;
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st_ref[1].repeat = 0;
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/* st 2 layer 0 - ref */
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st_ref[2].is_non_ref = 0;
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st_ref[2].temporal_id = 0;
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st_ref[2].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[2].ref_arg = 0;
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st_ref[2].repeat = 0;
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st_cfg_cnt = 3;
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tid0_loop = 2;
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mlvec_dbg_flow("tsvc2\n");
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} break;
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case 2 : {
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/* set tsvc3 st-ref struct */
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/* st 0 layer 0 - ref */
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st_ref[0].is_non_ref = 0;
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st_ref[0].temporal_id = 0;
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st_ref[0].ref_mode = REF_TO_TEMPORAL_LAYER;
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st_ref[0].ref_arg = 0;
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st_ref[0].repeat = 0;
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/* st 1 layer 2 - non-ref */
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st_ref[1].is_non_ref = 0;
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st_ref[1].temporal_id = 2;
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st_ref[1].ref_mode = REF_TO_TEMPORAL_LAYER;
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st_ref[1].ref_arg = 0;
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st_ref[1].repeat = 0;
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/* st 2 layer 1 - ref */
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st_ref[2].is_non_ref = 0;
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st_ref[2].temporal_id = 1;
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st_ref[2].ref_mode = REF_TO_TEMPORAL_LAYER;
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st_ref[2].ref_arg = 0;
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st_ref[2].repeat = 0;
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/* st 3 layer 2 - non-ref */
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st_ref[3].is_non_ref = 0;
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st_ref[3].temporal_id = 2;
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st_ref[3].ref_mode = REF_TO_TEMPORAL_LAYER;
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st_ref[3].ref_arg = 1;
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st_ref[3].repeat = 0;
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/* st 4 layer 0 - ref */
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st_ref[4].is_non_ref = 0;
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st_ref[4].temporal_id = 0;
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st_ref[4].ref_mode = REF_TO_TEMPORAL_LAYER;
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st_ref[4].ref_arg = 0;
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st_ref[4].repeat = 0;
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st_cfg_cnt = 5;
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tid0_loop = 4;
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mlvec_dbg_flow("tsvc3\n");
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} break;
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case 3 : {
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/* set tsvc3 st-ref struct */
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/* st 0 layer 0 - ref */
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st_ref[0].is_non_ref = 0;
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st_ref[0].temporal_id = 0;
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st_ref[0].ref_mode = REF_TO_TEMPORAL_LAYER;
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st_ref[0].ref_arg = 0;
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st_ref[0].repeat = 0;
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/* st 1 layer 3 - non-ref */
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st_ref[1].is_non_ref = 1;
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st_ref[1].temporal_id = 3;
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st_ref[1].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[1].ref_arg = 0;
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st_ref[1].repeat = 0;
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/* st 2 layer 2 - ref */
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st_ref[2].is_non_ref = 0;
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st_ref[2].temporal_id = 2;
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st_ref[2].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[2].ref_arg = 0;
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st_ref[2].repeat = 0;
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/* st 3 layer 3 - non-ref */
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st_ref[3].is_non_ref = 1;
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st_ref[3].temporal_id = 3;
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st_ref[3].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[3].ref_arg = 0;
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st_ref[3].repeat = 0;
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/* st 4 layer 1 - ref */
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st_ref[4].is_non_ref = 0;
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st_ref[4].temporal_id = 1;
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st_ref[4].ref_mode = REF_TO_TEMPORAL_LAYER;
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st_ref[4].ref_arg = 0;
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st_ref[4].repeat = 0;
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/* st 5 layer 3 - non-ref */
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st_ref[5].is_non_ref = 1;
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st_ref[5].temporal_id = 3;
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st_ref[5].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[5].ref_arg = 0;
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st_ref[5].repeat = 0;
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/* st 6 layer 2 - ref */
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st_ref[6].is_non_ref = 0;
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st_ref[6].temporal_id = 2;
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st_ref[6].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[6].ref_arg = 0;
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st_ref[6].repeat = 0;
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/* st 7 layer 3 - non-ref */
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st_ref[7].is_non_ref = 1;
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st_ref[7].temporal_id = 3;
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st_ref[7].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[7].ref_arg = 0;
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st_ref[7].repeat = 0;
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/* st 8 layer 0 - ref */
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st_ref[8].is_non_ref = 0;
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st_ref[8].temporal_id = 0;
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st_ref[8].ref_mode = REF_TO_PREV_REF_FRM;
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st_ref[8].ref_arg = 0;
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st_ref[8].repeat = 0;
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st_cfg_cnt = 9;
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tid0_loop = 8;
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mlvec_dbg_flow("tsvc4\n");
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} break;
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default : {
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mpp_err("invalid max temporal layer id %d\n", max_tid);
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} break;
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}
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if (ltr_frames) {
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RK_S32 i;
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lt_cfg_cnt = ltr_frames;
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mpp_assert(ltr_frames <= MPP_ENC_MAX_LT_REF_NUM);
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for (i = 0; i < ltr_frames; i++) {
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lt_ref[i].lt_idx = i;
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lt_ref[i].temporal_id = 0;
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lt_ref[i].ref_mode = REF_TO_PREV_LT_REF;
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lt_ref[i].lt_gap = 0;
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lt_ref[i].lt_delay = tid0_loop * i;
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}
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}
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if (lt_cfg_cnt)
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mpp_assert(st_cfg_cnt);
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mlvec_dbg_flow("lt_cfg_cnt %d st_cfg_cnt %d\n", lt_cfg_cnt, st_cfg_cnt);
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if (lt_cfg_cnt || st_cfg_cnt) {
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MppEncRefCfg ref = NULL;
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mpp_enc_ref_cfg_init(&ref);
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ret = mpp_enc_ref_cfg_set_cfg_cnt(ref, lt_cfg_cnt, st_cfg_cnt);
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ret = mpp_enc_ref_cfg_add_lt_cfg(ref, lt_cfg_cnt, lt_ref);
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ret = mpp_enc_ref_cfg_add_st_cfg(ref, st_cfg_cnt, st_ref);
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ret = mpp_enc_ref_cfg_set_keep_cpb(ref, 1);
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ret = mpp_enc_ref_cfg_check(ref);
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ret = mpi->control(mpp_ctx, MPP_ENC_SET_REF_CFG, ref);
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if (ret)
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mpp_err("mpi control enc set ref cfg failed ret %d\n", ret);
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mpp_enc_ref_cfg_deinit(&ref);
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} else {
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ret = mpi->control(mpp_ctx, MPP_ENC_SET_REF_CFG, NULL);
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if (ret)
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mpp_err("mpi control enc set ref cfg failed ret %d\n", ret);
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}
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mlvec_dbg_func("leave ctx %p ret %d\n", ctx, ret);
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return ret;
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}
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