/*
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* Copyright 2015 Rockchip Electronics Co. LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#define MODULE_TAG "hal_h264e_vepu2_v2"
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#include <string.h>
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#include "mpp_env.h"
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#include "mpp_mem.h"
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#include "mpp_frame.h"
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#include "mpp_common.h"
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#include "mpp_device.h"
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#include "mpp_rc.h"
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#include "mpp_enc_hal.h"
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#include "h264e_debug.h"
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#include "h264e_sps.h"
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#include "h264e_pps.h"
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#include "h264e_slice.h"
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#include "hal_h264e_debug.h"
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#include "hal_h264e_vpu_tbl.h"
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#include "hal_h264e_vepu_v2.h"
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#include "hal_h264e_vepu2_reg_tbl.h"
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typedef struct HalH264eVepu2Ctx_t {
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MppEncCfgSet *cfg;
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MppDev dev;
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RK_S32 frame_cnt;
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/* buffers management */
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HalH264eVepuBufs hw_bufs;
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/* preprocess config */
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HalH264eVepuPrep hw_prep;
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/* input / recon / refer address config */
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HalH264eVepuAddr hw_addr;
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VepuOffsetCfg hw_offset;
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/* macroblock ratecontrol config */
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HalH264eVepuMbRc hw_mbrc;
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/* syntax for input from enc_impl */
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RK_U32 updated;
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H264eSps *sps;
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H264ePps *pps;
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H264eSlice *slice;
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H264eFrmInfo *frms;
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H264eReorderInfo *reorder;
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H264eMarkingInfo *marking;
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H264ePrefixNal *prefix;
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/* special TSVC stream header fixup */
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HalH264eVepuStreamAmend amend;
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/* vepu2 macroblock ratecontrol context */
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HalH264eVepuMbRcCtx rc_ctx;
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H264eVpu2RegSet regs_set;
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H264eVpu2RegSet regs_get;
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} HalH264eVepu2Ctx;
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static MPP_RET hal_h264e_vepu2_deinit_v2(void *hal)
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{
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HalH264eVepu2Ctx *p = (HalH264eVepu2Ctx *)hal;
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hal_h264e_dbg_func("enter %p\n", p);
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if (p->dev) {
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mpp_dev_deinit(p->dev);
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p->dev = NULL;
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}
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h264e_vepu_buf_deinit(&p->hw_bufs);
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if (p->rc_ctx) {
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h264e_vepu_mbrc_deinit(p->rc_ctx);
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p->rc_ctx = NULL;
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}
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h264e_vepu_stream_amend_deinit(&p->amend);
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hal_h264e_dbg_func("leave %p\n", p);
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return MPP_OK;
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}
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static MPP_RET hal_h264e_vepu2_init_v2(void *hal, MppEncHalCfg *cfg)
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{
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HalH264eVepu2Ctx *p = (HalH264eVepu2Ctx *)hal;
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MPP_RET ret = MPP_OK;
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hal_h264e_dbg_func("enter %p\n", p);
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p->cfg = cfg->cfg;
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/* update output to MppEnc */
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cfg->type = VPU_CLIENT_VEPU2;
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ret = mpp_dev_init(&cfg->dev, cfg->type);
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if (ret) {
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mpp_err_f("mpp_dev_init failed ret: %d\n", ret);
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goto DONE;
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}
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p->dev = cfg->dev;
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ret = h264e_vepu_buf_init(&p->hw_bufs);
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if (ret) {
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mpp_err_f("init vepu buffer failed ret: %d\n", ret);
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goto DONE;
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}
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ret = h264e_vepu_mbrc_init(&p->rc_ctx, &p->hw_mbrc);
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if (ret) {
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mpp_err_f("init mb rate control failed ret: %d\n", ret);
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goto DONE;
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}
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/* create buffer to TSVC stream */
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h264e_vepu_stream_amend_init(&p->amend);
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DONE:
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if (ret)
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hal_h264e_vepu2_deinit_v2(hal);
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hal_h264e_dbg_func("leave %p\n", p);
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return ret;
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}
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static RK_U32 update_vepu2_syntax(HalH264eVepu2Ctx *ctx, MppSyntax *syntax)
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{
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H264eSyntaxDesc *desc = syntax->data;
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RK_S32 syn_num = syntax->number;
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RK_U32 updated = 0;
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RK_S32 i;
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for (i = 0; i < syn_num; i++, desc++) {
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switch (desc->type) {
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case H264E_SYN_CFG : {
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hal_h264e_dbg_detail("update cfg");
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ctx->cfg = desc->p;
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} break;
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case H264E_SYN_SPS : {
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hal_h264e_dbg_detail("update sps");
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ctx->sps = desc->p;
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} break;
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case H264E_SYN_PPS : {
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hal_h264e_dbg_detail("update pps");
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ctx->pps = desc->p;
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} break;
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case H264E_SYN_DPB : {
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hal_h264e_dbg_detail("update dpb");
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} break;
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case H264E_SYN_SLICE : {
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hal_h264e_dbg_detail("update slice");
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ctx->slice = desc->p;
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} break;
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case H264E_SYN_FRAME : {
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hal_h264e_dbg_detail("update frames");
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ctx->frms = desc->p;
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} break;
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case H264E_SYN_PREFIX : {
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hal_h264e_dbg_detail("update prefix nal");
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ctx->prefix = desc->p;
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} break;
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default : {
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mpp_log_f("invalid syntax type %d\n", desc->type);
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} break;
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}
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updated |= SYN_TYPE_FLAG(desc->type);
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}
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return updated;
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}
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static MPP_RET hal_h264e_vepu2_get_task_v2(void *hal, HalEncTask *task)
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{
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HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
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RK_U32 updated = update_vepu2_syntax(ctx, &task->syntax);
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MppEncPrepCfg *prep = &ctx->cfg->prep;
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HalH264eVepuPrep *hw_prep = &ctx->hw_prep;
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HalH264eVepuAddr *hw_addr = &ctx->hw_addr;
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HalH264eVepuBufs *hw_bufs = &ctx->hw_bufs;
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VepuOffsetCfg *hw_offset = &ctx->hw_offset;
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H264eFrmInfo *frms = ctx->frms;
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hal_h264e_dbg_func("enter %p\n", hal);
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if (updated & SYN_TYPE_FLAG(H264E_SYN_CFG)) {
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h264e_vepu_buf_set_frame_size(hw_bufs, prep->width, prep->height);
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/* preprocess setup */
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h264e_vepu_prep_setup(hw_prep, prep);
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h264e_vepu_mbrc_setup(ctx->rc_ctx, ctx->cfg);
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}
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if (updated & SYN_TYPE_FLAG(H264E_SYN_SLICE)) {
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H264eSlice *slice = ctx->slice;
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h264e_vepu_buf_set_cabac_idc(hw_bufs, slice->cabac_init_idc);
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}
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h264e_vepu_prep_get_addr(hw_prep, task->input, &hw_addr->orig);
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MppBuffer recn = h264e_vepu_buf_get_frame_buffer(hw_bufs, frms->curr_idx);
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MppBuffer refr = h264e_vepu_buf_get_frame_buffer(hw_bufs, frms->refr_idx);
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hw_addr->recn[0] = mpp_buffer_get_fd(recn);
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hw_addr->refr[0] = mpp_buffer_get_fd(refr);
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hw_addr->recn[1] = hw_addr->recn[0];
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hw_addr->refr[1] = hw_addr->refr[0];
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hw_offset->fmt = prep->format;
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hw_offset->width = prep->width;
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hw_offset->height = prep->height;
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hw_offset->hor_stride = prep->hor_stride;
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hw_offset->ver_stride = prep->ver_stride;
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hw_offset->offset_x = mpp_frame_get_offset_x(task->frame);
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hw_offset->offset_y = mpp_frame_get_offset_y(task->frame);
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get_vepu_offset_cfg(hw_offset);
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h264e_vepu_stream_amend_config(&ctx->amend, task->packet, ctx->cfg,
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ctx->slice, ctx->prefix);
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hal_h264e_dbg_func("leave %p\n", hal);
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return MPP_OK;
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}
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static RK_S32 setup_output_packet(HalH264eVepu2Ctx *ctx, RK_U32 *reg, MppBuffer buf, RK_U32 offset)
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{
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RK_U32 offset8 = offset & (~0x7);
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RK_S32 fd = mpp_buffer_get_fd(buf);
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RK_U32 hdr_rem_msb = 0;
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RK_U32 hdr_rem_lsb = 0;
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RK_U32 limit = 0;
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if (offset) {
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RK_U8 *buf32 = (RK_U8 *)mpp_buffer_get_ptr(buf) + offset8;
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hdr_rem_msb = MPP_RB32(buf32);
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hdr_rem_lsb = MPP_RB32(buf32 + 4);
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}
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hal_h264e_dbg_detail("offset %d offset8 %d\n", offset, offset8);
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H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_STREAM, fd);
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mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_OUTPUT_STREAM >> 2, offset8);
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/* output buffer size is 64 bit address then 8 multiple size */
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limit = mpp_buffer_get_size(buf);
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limit -= offset8;
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limit >>= 3;
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limit &= ~7;
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H264E_HAL_SET_REG(reg, VEPU_REG_STR_BUF_LIMIT, limit);
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hal_h264e_dbg_detail("msb %08x lsb %08x", hdr_rem_msb, hdr_rem_lsb);
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H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_MSB, hdr_rem_msb);
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H264E_HAL_SET_REG(reg, VEPU_REG_STR_HDR_REM_LSB, hdr_rem_lsb);
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return (offset - offset8) * 8;
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}
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static MPP_RET hal_h264e_vepu2_gen_regs_v2(void *hal, HalEncTask *task)
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{
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//MPP_RET ret = MPP_OK;
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HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
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HalH264eVepuBufs *hw_bufs = &ctx->hw_bufs;
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HalH264eVepuPrep *hw_prep = &ctx->hw_prep;
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HalH264eVepuAddr *hw_addr = &ctx->hw_addr;
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HalH264eVepuMbRc *hw_mbrc = &ctx->hw_mbrc;
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VepuOffsetCfg *hw_offset = &ctx->hw_offset;
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EncRcTaskInfo *rc_info = &task->rc_task->info;
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EncFrmStatus *frm = &task->rc_task->frm;
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H264eSps *sps = ctx->sps;
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H264ePps *pps = ctx->pps;
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H264eSlice *slice = ctx->slice;
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RK_U32 *reg = ctx->regs_set.val;
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RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
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RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
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RK_U32 offset = mpp_packet_get_length(task->packet);
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RK_U32 first_free_bit = 0;
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RK_U32 val = 0;
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RK_S32 i = 0;
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hw_mbrc->qp_init = rc_info->quality_target;
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hw_mbrc->qp_max = rc_info->quality_max;
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hw_mbrc->qp_min = rc_info->quality_min;
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hal_h264e_dbg_func("enter %p\n", hal);
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hal_h264e_dbg_detail("frame %d generate regs now", frm->seq_idx);
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// prepare mb rc config
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h264e_vepu_mbrc_prepare(ctx->rc_ctx, &ctx->hw_mbrc, task->rc_task);
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h264e_vepu_slice_split_cfg(ctx->slice, &ctx->hw_mbrc, task->rc_task, ctx->cfg);
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/* setup output address with offset */
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first_free_bit = setup_output_packet(ctx, reg, task->output, offset);
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/* set extra byte for header */
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hw_mbrc->hdr_strm_size = offset;
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hw_mbrc->hdr_free_size = first_free_bit / 8;
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hw_mbrc->out_strm_size = 0;
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/*
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* The hardware needs only the value for luma plane, because
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* values of other planes are calculated internally based on
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* format setting.
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*/
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val = VEPU_REG_INTRA_AREA_TOP(mb_h)
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| VEPU_REG_INTRA_AREA_BOTTOM(mb_h)
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| VEPU_REG_INTRA_AREA_LEFT(mb_w)
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| VEPU_REG_INTRA_AREA_RIGHT(mb_w);
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H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_AREA_CTRL, val);
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val = VEPU_REG_AXI_CTRL_READ_ID(0);
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val |= VEPU_REG_AXI_CTRL_WRITE_ID(0);
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val |= VEPU_REG_AXI_CTRL_BURST_LEN(16);
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val |= VEPU_REG_AXI_CTRL_INCREMENT_MODE(0);
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val |= VEPU_REG_AXI_CTRL_BIRST_DISCARD(0);
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H264E_HAL_SET_REG(reg, VEPU_REG_AXI_CTRL, val);
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H264E_HAL_SET_REG(reg, VEPU_QP_ADJUST_MAD_DELTA_ROI,
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hw_mbrc->mad_qp_change);
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val = 0;
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if (mb_w * mb_h > 3600)
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val = VEPU_REG_DISABLE_QUARTER_PIXEL_MV;
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val |= VEPU_REG_CABAC_INIT_IDC(slice->cabac_init_idc);
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if (pps->entropy_coding_mode)
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val |= VEPU_REG_ENTROPY_CODING_MODE;
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if (pps->transform_8x8_mode)
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val |= VEPU_REG_H264_TRANS8X8_MODE;
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if (sps->profile_idc > 31)
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val |= VEPU_REG_H264_INTER4X4_MODE;
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/*reg |= VEPU_REG_H264_STREAM_MODE;*/
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val |= VEPU_REG_H264_SLICE_SIZE(hw_mbrc->slice_size_mb_rows);
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H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL0, val);
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RK_U32 scaler = MPP_MAX(1, 200 / (mb_w + mb_h));
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RK_U32 skip_penalty = MPP_MIN(255, h264_skip_sad_penalty[hw_mbrc->qp_init] * scaler);
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RK_U32 overfill_r = (hw_prep->src_w & 0x0f) ?
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((16 - (hw_prep->src_w & 0x0f)) / 4) : 0;
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RK_U32 overfill_b = (hw_prep->src_h & 0x0f) ?
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(16 - (hw_prep->src_h & 0x0f)) : 0;
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val = VEPU_REG_STREAM_START_OFFSET(first_free_bit) |
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VEPU_REG_SKIP_MACROBLOCK_PENALTY(skip_penalty) |
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VEPU_REG_IN_IMG_CTRL_OVRFLR_D4(overfill_r) |
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VEPU_REG_IN_IMG_CTRL_OVRFLB(overfill_b);
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H264E_HAL_SET_REG(reg, VEPU_REG_ENC_OVER_FILL_STRM_OFFSET, val);
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// When offset is zero row length should be total 16 aligned width
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val = VEPU_REG_IN_IMG_CHROMA_OFFSET(0)
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| VEPU_REG_IN_IMG_LUMA_OFFSET(0)
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| VEPU_REG_IN_IMG_CTRL_ROW_LEN(hw_prep->pixel_stride);
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H264E_HAL_SET_REG(reg, VEPU_REG_INPUT_LUMA_INFO, val);
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val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[0])
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| VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[1]);
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H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(0), val);
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val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[2])
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| VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[3]);
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H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(1), val);
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val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[4])
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| VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[5]);
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H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(2), val);
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val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[6])
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| VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[7]);
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H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(3), val);
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val = VEPU_REG_CHECKPOINT_CHECK1(hw_mbrc->cp_target[8])
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| VEPU_REG_CHECKPOINT_CHECK0(hw_mbrc->cp_target[9]);
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H264E_HAL_SET_REG(reg, VEPU_REG_CHECKPOINT(4), val);
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val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[0])
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| VEPU_REG_CHKPT_WORD_ERR_CHK0(hw_mbrc->cp_error[1]);
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H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(0), val);
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val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[2])
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| VEPU_REG_CHKPT_WORD_ERR_CHK0(hw_mbrc->cp_error[3]);
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H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(1), val);
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val = VEPU_REG_CHKPT_WORD_ERR_CHK1(hw_mbrc->cp_error[4])
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| VEPU_REG_CHKPT_WORD_ERR_CHK0(hw_mbrc->cp_error[5]);
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H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_WORD_ERR(2), val);
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val = VEPU_REG_CHKPT_DELTA_QP_CHK6(hw_mbrc->cp_delta_qp[6])
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| VEPU_REG_CHKPT_DELTA_QP_CHK5(hw_mbrc->cp_delta_qp[5])
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| VEPU_REG_CHKPT_DELTA_QP_CHK4(hw_mbrc->cp_delta_qp[4])
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| VEPU_REG_CHKPT_DELTA_QP_CHK3(hw_mbrc->cp_delta_qp[3])
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| VEPU_REG_CHKPT_DELTA_QP_CHK2(hw_mbrc->cp_delta_qp[2])
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| VEPU_REG_CHKPT_DELTA_QP_CHK1(hw_mbrc->cp_delta_qp[1])
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| VEPU_REG_CHKPT_DELTA_QP_CHK0(hw_mbrc->cp_delta_qp[0]);
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H264E_HAL_SET_REG(reg, VEPU_REG_CHKPT_DELTA_QP, val);
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val = VEPU_REG_MAD_THRESHOLD(hw_mbrc->mad_threshold)
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| VEPU_REG_IN_IMG_CTRL_FMT(hw_prep->src_fmt)
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| VEPU_REG_IN_IMG_ROTATE_MODE(0)
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| VEPU_REG_SIZE_TABLE_PRESENT; //FIXED
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H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL1, val);
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val = VEPU_REG_INTRA16X16_MODE(h264_intra16_favor[hw_mbrc->qp_init])
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| VEPU_REG_INTER_MODE(h264_inter_favor[hw_mbrc->qp_init]);
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H264E_HAL_SET_REG(reg, VEPU_REG_INTRA_INTER_MODE, val);
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val = VEPU_REG_PPS_INIT_QP(pps->pic_init_qp)
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| VEPU_REG_SLICE_FILTER_ALPHA(slice->slice_alpha_c0_offset_div2)
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| VEPU_REG_SLICE_FILTER_BETA(slice->slice_beta_offset_div2)
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| VEPU_REG_CHROMA_QP_OFFSET(pps->chroma_qp_index_offset)
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| VEPU_REG_IDR_PIC_ID(slice->idr_pic_id);
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if (slice->disable_deblocking_filter_idc)
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val |= VEPU_REG_FILTER_DISABLE;
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if (pps->constrained_intra_pred)
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val |= VEPU_REG_CONSTRAINED_INTRA_PREDICTION;
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H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL2, val);
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H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_NEXT_PIC, 0);
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H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_MV_OUT, 0);
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MppBuffer cabac_table = hw_bufs->cabac_table;
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RK_S32 cabac_table_fd = cabac_table ? mpp_buffer_get_fd(cabac_table) : 0;
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H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_CABAC_TBL, cabac_table_fd);
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val = VEPU_REG_ROI1_TOP_MB(mb_h)
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| VEPU_REG_ROI1_BOTTOM_MB(mb_h)
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| VEPU_REG_ROI1_LEFT_MB(mb_w)
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| VEPU_REG_ROI1_RIGHT_MB(mb_w);
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H264E_HAL_SET_REG(reg, VEPU_REG_ROI1, val);
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val = VEPU_REG_ROI2_TOP_MB(mb_h)
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| VEPU_REG_ROI2_BOTTOM_MB(mb_h)
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| VEPU_REG_ROI2_LEFT_MB(mb_w)
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| VEPU_REG_ROI2_RIGHT_MB(mb_w);
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H264E_HAL_SET_REG(reg, VEPU_REG_ROI2, val);
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H264E_HAL_SET_REG(reg, VEPU_REG_STABLILIZATION_OUTPUT, 0);
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val = VEPU_REG_RGB2YUV_CONVERSION_COEFB(hw_prep->color_conversion_coeff_b)
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| VEPU_REG_RGB2YUV_CONVERSION_COEFA(hw_prep->color_conversion_coeff_a);
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H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF1, val);
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val = VEPU_REG_RGB2YUV_CONVERSION_COEFE(hw_prep->color_conversion_coeff_e)
|
| VEPU_REG_RGB2YUV_CONVERSION_COEFC(hw_prep->color_conversion_coeff_c);
|
H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF2, val);
|
|
val = VEPU_REG_RGB2YUV_CONVERSION_COEFF(hw_prep->color_conversion_coeff_f);
|
H264E_HAL_SET_REG(reg, VEPU_REG_RGB2YUV_CONVERSION_COEF3, val);
|
|
val = VEPU_REG_RGB_MASK_B_MSB(hw_prep->b_mask_msb)
|
| VEPU_REG_RGB_MASK_G_MSB(hw_prep->g_mask_msb)
|
| VEPU_REG_RGB_MASK_R_MSB(hw_prep->r_mask_msb);
|
H264E_HAL_SET_REG(reg, VEPU_REG_RGB_MASK_MSB, val); //FIXED
|
|
{
|
RK_U32 diff_mv_penalty[3] = {0};
|
diff_mv_penalty[0] = h264_diff_mv_penalty4p[hw_mbrc->qp_init];
|
diff_mv_penalty[1] = h264_diff_mv_penalty[hw_mbrc->qp_init];
|
diff_mv_penalty[2] = h264_diff_mv_penalty[hw_mbrc->qp_init];
|
|
val = VEPU_REG_1MV_PENALTY(diff_mv_penalty[1])
|
| VEPU_REG_QMV_PENALTY(diff_mv_penalty[2])
|
| VEPU_REG_4MV_PENALTY(diff_mv_penalty[0]);
|
}
|
|
val |= VEPU_REG_SPLIT_MV_MODE_EN;
|
H264E_HAL_SET_REG(reg, VEPU_REG_MV_PENALTY, val);
|
|
val = VEPU_REG_H264_LUMA_INIT_QP(hw_mbrc->qp_init)
|
| VEPU_REG_H264_QP_MAX(hw_mbrc->qp_max)
|
| VEPU_REG_H264_QP_MIN(hw_mbrc->qp_min)
|
| VEPU_REG_H264_CHKPT_DISTANCE(hw_mbrc->cp_distance_mbs);
|
H264E_HAL_SET_REG(reg, VEPU_REG_QP_VAL, val);
|
|
val = VEPU_REG_ZERO_MV_FAVOR_D2(10);
|
H264E_HAL_SET_REG(reg, VEPU_REG_MVC_RELATE, val);
|
|
val = VEPU_REG_OUTPUT_SWAP32
|
| VEPU_REG_OUTPUT_SWAP16
|
| VEPU_REG_OUTPUT_SWAP8
|
| VEPU_REG_INPUT_SWAP8_(hw_prep->swap_8_in)
|
| VEPU_REG_INPUT_SWAP16_(hw_prep->swap_16_in)
|
| VEPU_REG_INPUT_SWAP32_(hw_prep->swap_32_in);
|
H264E_HAL_SET_REG(reg, VEPU_REG_DATA_ENDIAN, val);
|
|
val = VEPU_REG_PPS_ID(pps->pps_id)
|
| VEPU_REG_INTRA_PRED_MODE(h264_prev_mode_favor[hw_mbrc->qp_init])
|
| VEPU_REG_FRAME_NUM(slice->frame_num);
|
H264E_HAL_SET_REG(reg, VEPU_REG_ENC_CTRL3, val);
|
|
val = VEPU_REG_INTERRUPT_TIMEOUT_EN;
|
H264E_HAL_SET_REG(reg, VEPU_REG_INTERRUPT, val);
|
|
{
|
RK_U8 dmv_penalty[128] = {0};
|
RK_U8 dmv_qpel_penalty[128] = {0};
|
|
for (i = 0; i < 128; i++) {
|
dmv_penalty[i] = i;
|
dmv_qpel_penalty[i] = MPP_MIN(255, exp_golomb_signed(i));
|
}
|
|
for (i = 0; i < 128; i += 4) {
|
val = VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i], 3);
|
val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 1], 2);
|
val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 2], 1);
|
val |= VEPU_REG_DMV_PENALTY_TABLE_BIT(dmv_penalty[i + 3], 0);
|
H264E_HAL_SET_REG(reg, VEPU_REG_DMV_PENALTY_TBL(i / 4), val);
|
|
val = VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(
|
dmv_qpel_penalty[i], 3);
|
val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(
|
dmv_qpel_penalty[i + 1], 2);
|
val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(
|
dmv_qpel_penalty[i + 2], 1);
|
val |= VEPU_REG_DMV_Q_PIXEL_PENALTY_TABLE_BIT(
|
dmv_qpel_penalty[i + 3], 0);
|
H264E_HAL_SET_REG(reg, VEPU_REG_DMV_Q_PIXEL_PENALTY_TBL(i / 4), val);
|
}
|
}
|
|
/* set buffers addr */
|
H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_LUMA, hw_addr->orig[0]);
|
if (hw_offset->offset_byte[0])
|
mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_LUMA >> 2,
|
hw_offset->offset_byte[0]);
|
H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_CB, hw_addr->orig[1]);
|
if (hw_offset->offset_byte[1])
|
mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CB >> 2,
|
hw_offset->offset_byte[1]);
|
H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_IN_CR, hw_addr->orig[2]);
|
if (hw_offset->offset_byte[2])
|
mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_IN_CR >> 2,
|
hw_offset->offset_byte[2]);
|
|
MppBuffer nal_size_table = h264e_vepu_buf_get_nal_size_table(hw_bufs);
|
RK_S32 nal_size_table_fd = nal_size_table ? mpp_buffer_get_fd(nal_size_table) : 0;
|
|
H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_OUTPUT_CTRL, nal_size_table_fd);
|
|
H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REC_LUMA, hw_addr->recn[0]);
|
H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REC_CHROMA, hw_addr->recn[1]);
|
mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_REC_CHROMA >> 2, hw_bufs->yuv_size);
|
H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REF_LUMA, hw_addr->refr[0]);
|
H264E_HAL_SET_REG(reg, VEPU_REG_ADDR_REF_CHROMA, hw_addr->refr[1]);
|
mpp_dev_set_reg_offset(ctx->dev, VEPU_REG_ADDR_REF_CHROMA >> 2, hw_bufs->yuv_size);
|
|
/* set important encode mode info */
|
val = VEPU_REG_MB_HEIGHT(mb_h)
|
| VEPU_REG_MB_WIDTH(mb_w)
|
| VEPU_REG_PIC_TYPE(slice->idr_flag)
|
| VEPU_REG_ENCODE_FORMAT(3)
|
| VEPU_REG_ENCODE_ENABLE;
|
H264E_HAL_SET_REG(reg, VEPU_REG_ENCODE_START, val);
|
|
ctx->frame_cnt++;
|
|
hal_h264e_dbg_func("leave %p\n", hal);
|
return MPP_OK;
|
}
|
|
static MPP_RET hal_h264e_vepu2_start_v2(void *hal, HalEncTask *task)
|
{
|
MPP_RET ret = MPP_OK;
|
HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
|
(void)task;
|
|
hal_h264e_dbg_func("enter %p\n", hal);
|
|
if (ctx->dev) {
|
MppDevRegWrCfg wr_cfg;
|
MppDevRegRdCfg rd_cfg;
|
RK_U32 reg_size = sizeof(ctx->regs_set);
|
|
do {
|
wr_cfg.reg = &ctx->regs_set;
|
wr_cfg.size = reg_size;
|
wr_cfg.offset = 0;
|
|
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_WR, &wr_cfg);
|
if (ret) {
|
mpp_err_f("set register write failed %d\n", ret);
|
break;
|
}
|
|
rd_cfg.reg = &ctx->regs_get;
|
rd_cfg.size = reg_size;
|
rd_cfg.offset = 0;
|
|
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_REG_RD, &rd_cfg);
|
if (ret) {
|
mpp_err_f("set register read failed %d\n", ret);
|
break;
|
}
|
|
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_SEND, NULL);
|
if (ret) {
|
mpp_err_f("send cmd failed %d\n", ret);
|
break;
|
}
|
} while (0);
|
} else
|
mpp_err("invalid NULL device ctx\n");
|
|
hal_h264e_dbg_func("leave %p\n", hal);
|
|
return ret;
|
}
|
|
static void h264e_vepu2_get_mbrc(HalH264eVepuMbRc *mb_rc, H264eVpu2RegSet *reg)
|
{
|
RK_S32 i = 0;
|
RK_U32 cpt_prev = 0;
|
RK_U32 overflow = 0;
|
RK_U32 cpt_idx = VEPU_REG_CHECKPOINT(0) / 4;
|
RK_U32 *reg_val = reg->val;
|
|
mb_rc->hw_status = reg_val[VEPU_REG_INTERRUPT / 4];
|
mb_rc->out_strm_size = reg_val[VEPU_REG_STR_BUF_LIMIT / 4] / 8 - mb_rc->hdr_free_size;
|
mb_rc->qp_sum = ((reg_val[VEPU_REG_QP_SUM_DIV2 / 4] >> 11) & 0x001fffff) * 2;
|
mb_rc->less_mad_count = (reg_val[VEPU_REG_MB_CTRL / 4] >> 16) & 0xffff;
|
mb_rc->rlc_count = reg_val[VEPU_REG_RLC_SUM / 4] & 0x3fffff;
|
|
for (i = 0; i < VEPU_CHECK_POINTS_MAX; i++) {
|
RK_U32 cpt = VEPU_REG_CHECKPOINT_RESULT(reg_val[cpt_idx]);
|
|
if (cpt < cpt_prev)
|
overflow += (1 << 21);
|
|
cpt_prev = cpt;
|
mb_rc->cp_usage[i] = cpt + overflow;
|
cpt_idx += (i & 1);
|
}
|
}
|
|
static MPP_RET hal_h264e_vepu2_wait_v2(void *hal, HalEncTask *task)
|
{
|
HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
|
HalH264eVepuMbRc *hw_mbrc = &ctx->hw_mbrc;
|
MPP_RET ret = MPP_NOK;
|
(void) task;
|
|
hal_h264e_dbg_func("enter %p\n", hal);
|
|
if (ctx->dev) {
|
ret = mpp_dev_ioctl(ctx->dev, MPP_DEV_CMD_POLL, NULL);
|
if (ret)
|
mpp_err_f("poll cmd failed %d\n", ret);
|
} else {
|
mpp_err("invalid NULL device ctx\n");
|
return ret;
|
}
|
|
h264e_vepu2_get_mbrc(hw_mbrc, &ctx->regs_get);
|
h264e_vepu_mbrc_update(ctx->rc_ctx, hw_mbrc);
|
|
{
|
HalH264eVepuStreamAmend *amend = &ctx->amend;
|
if (amend->enable) {
|
amend->old_length = hw_mbrc->out_strm_size;
|
h264e_vepu_stream_amend_proc(amend);
|
ctx->hw_mbrc.out_strm_size = amend->new_length;
|
} else if (amend->prefix) {
|
/* check prefix value */
|
amend->old_length = hw_mbrc->out_strm_size;
|
h264e_vepu_stream_amend_sync_ref_idc(amend);
|
}
|
}
|
|
task->hw_length += ctx->hw_mbrc.out_strm_size;
|
|
hal_h264e_dbg_func("leave %p\n", hal);
|
|
return MPP_OK;
|
}
|
|
static MPP_RET hal_h264e_vepu2_ret_task_v2(void *hal, HalEncTask *task)
|
{
|
HalH264eVepu2Ctx *ctx = (HalH264eVepu2Ctx *)hal;
|
EncRcTaskInfo *rc_info = &task->rc_task->info;
|
RK_U32 mb_w = ctx->sps->pic_width_in_mbs;
|
RK_U32 mb_h = ctx->sps->pic_height_in_mbs;
|
RK_U32 mbs = mb_w * mb_h;
|
|
hal_h264e_dbg_func("enter %p\n", hal);
|
|
task->length += task->hw_length;
|
|
rc_info->bit_real = task->hw_length * 8;
|
rc_info->quality_real = ctx->hw_mbrc.qp_sum / mbs;
|
|
hal_h264e_dbg_rc("real bit %d quality %d\n", rc_info->bit_real, rc_info->quality_real);
|
|
task->hal_ret.data = rc_info;
|
task->hal_ret.number = 1;
|
|
hal_h264e_dbg_func("leave %p\n", hal);
|
|
return MPP_OK;
|
}
|
|
const MppEncHalApi hal_h264e_vepu2 = {
|
.name = "hal_h264e_vepu2",
|
.coding = MPP_VIDEO_CodingAVC,
|
.ctx_size = sizeof(HalH264eVepu2Ctx),
|
.flag = 0,
|
.init = hal_h264e_vepu2_init_v2,
|
.deinit = hal_h264e_vepu2_deinit_v2,
|
.prepare = NULL,
|
.get_task = hal_h264e_vepu2_get_task_v2,
|
.gen_regs = hal_h264e_vepu2_gen_regs_v2,
|
.start = hal_h264e_vepu2_start_v2,
|
.wait = hal_h264e_vepu2_wait_v2,
|
.part_start = NULL,
|
.part_wait = NULL,
|
.ret_task = hal_h264e_vepu2_ret_task_v2,
|
};
|
