#ifndef _CH343_H
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#define _CH343_H
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/*
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* Baud rate and default timeout
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*/
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#define DEFAULT_BAUD_RATE 9600
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#define DEFAULT_TIMEOUT 2000
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/*
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* CMSPAR, some architectures can't have space and mark parity.
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*/
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#ifndef CMSPAR
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#define CMSPAR 0
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#endif
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/*
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* Major and minor numbers.
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*/
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#define CH343_TTY_MAJOR 170
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#define CH343_TTY_MINORS 256
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#define USB_MINOR_BASE 70
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/*
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* Requests.
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*/
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#define USB_RT_CH343 (USB_TYPE_CLASS | USB_RECIP_INTERFACE)
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#define CMD_R 0x95
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#define CMD_W 0x9A
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#define CMD_C1 0xA1
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#define CMD_C2 0xA4
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#define CMD_C3 0x05
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#define CMD_C4 0xA8
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#define CMD_C5 0x5E
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#define CMD_C6 0x5F
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#define CH343_CTO_O 0x10
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#define CH343_CTO_D 0x20
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#define CH343_CTO_R 0x40
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#define CH343_CTO_A 0x80
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#define CH343_CTI_C 0x01
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#define CH343_CTI_DS 0x02
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#define CH343_CTI_R 0x04
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#define CH343_CTI_DC 0x08
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#define CH343_CTI_ST 0x0f
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#define CH343_CTT_M 0x08
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#define CH343_CTT_F 0x44
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#define CH343_CTT_P 0x04
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#define CH343_CTT_O 0x02
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#define CH343_LO 0x02
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#define CH343_LE 0x04
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#define CH343_LB
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#define CH343_LP 0x00
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#define CH343_LF 0x40
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#define CH343_LM 0x08
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#define CH343_L_R_CT 0x80
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#define CH343_L_R_CL 0x04
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#define CH343_L_R_T 0x08
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#define CH343_L_E_R 0x80
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#define CH343_L_E_T 0x40
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#define CH343_L_P_S 0x38
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#define CH343_L_P_M 0x28
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#define CH343_L_P_E 0x18
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#define CH343_L_P_O 0x08
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#define CH343_L_SB 0x04
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#define CH343_L_C8 0x03
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#define CH343_L_C7 0x02
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#define CH343_L_C6 0x01
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#define CH343_L_C5 0x00
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#define CH343_N_B 0x80
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#define CH343_N_AB 0x10
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/*
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* Internal driver structures.
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*/
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/*
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* The only reason to have several buffers is to accommodate assumptions
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* in line disciplines. They ask for empty space amount, receive our URB size,
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* and proceed to issue several 1-character writes, assuming they will fit.
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* The very first write takes a complete URB. Fortunately, this only happens
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* when processing onlcr, so we only need 2 buffers. These values must be
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* powers of 2.
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*/
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#define CH343_NW 16
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#define CH343_NR 16
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struct ch343_wb {
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unsigned char *buf;
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dma_addr_t dmah;
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int len;
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int use;
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struct urb *urb;
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struct ch343 *instance;
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};
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struct ch343_rb {
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int size;
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unsigned char *base;
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dma_addr_t dma;
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int index;
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struct ch343 *instance;
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};
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struct usb_ch343_line_coding {
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__u32 dwDTERate;
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__u8 bCharFormat;
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#define USB_CH343_1_STOP_BITS 0
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#define USB_CH343_1_5_STOP_BITS 1
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#define USB_CH343_2_STOP_BITS 2
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__u8 bParityType;
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#define USB_CH343_NO_PARITY 0
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#define USB_CH343_ODD_PARITY 1
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#define USB_CH343_EVEN_PARITY 2
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#define USB_CH343_MARK_PARITY 3
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#define USB_CH343_SPACE_PARITY 4
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__u8 bDataBits;
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} __attribute__((packed));
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typedef enum {
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CHIP_CH342F = 0x00,
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CHIP_CH342K,
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CHIP_CH343GP,
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CHIP_CH343G_AUTOBAUD,
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CHIP_CH343K,
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CHIP_CH343J,
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CHIP_CH344L,
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CHIP_CH344L_V2,
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CHIP_CH344Q,
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CHIP_CH347T,
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CHIP_CH9101UH,
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CHIP_CH9101RY,
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CHIP_CH9102F,
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CHIP_CH9102X,
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CHIP_CH9103M,
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CHIP_CH9104L,
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} CHIPTYPE;
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struct gpioinfo {
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int group;
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int pin;
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};
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struct ch343_gpio {
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int gpiocount;
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struct gpioinfo io[64];
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};
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struct ch343_gpio ch343_gpios[] = {
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{ 0, {}},
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{ 0, {}},
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{ 0, {}},
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{ 0, {}},
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{ 0, {}},
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{ 0, {}},
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/* CH344L */
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{ 8, {}},
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/* CH344L-V2 */
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{ 8, {}},
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/* CH344Q */
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{ 8, {}},
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/* CH347T */
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{ 4, {}},
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/* CH9101UH */
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{ 5, {{3, 2}, {3, 3}, {1, 3}, {1, 2}, {1, 5}, {2, 4}}},
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/* CH9101RY */
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{ 4, {{1, 3}, {3, 3}, {3, 2}, {2, 4}}},
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/* CH9102F */
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{ 5, {{2, 1}, {2, 7}, {2, 4}, {2, 6}, {2, 3}}},
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/* CH9102X */
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{ 6, {{2, 3}, {2, 5}, {2, 1}, {2, 7}, {3, 0}, {2, 2}}},
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/* CH9103M */
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{12, {{1, 3}, {1, 2}, {3, 2}, {2, 6}, {1, 0}, {1, 6}, {2, 3}, {2, 5}, {3, 0}, {2, 2}, {1, 5}, {2, 4}}},
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/* CH9104L */
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{24, {}},
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};
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struct ch343 {
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struct usb_device *dev; /* the corresponding usb device */
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struct usb_interface *control; /* control interface */
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struct usb_interface *data; /* data interface */
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struct tty_port port; /* our tty port data */
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struct urb *ctrlurb; /* urbs */
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u8 *ctrl_buffer; /* buffers of urbs */
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dma_addr_t ctrl_dma; /* dma handles of buffers */
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struct ch343_wb wb[CH343_NW];
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unsigned long read_urbs_free;
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struct urb *read_urbs[CH343_NR];
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struct ch343_rb read_buffers[CH343_NR];
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int rx_buflimit;
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int rx_endpoint;
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spinlock_t read_lock;
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int write_used; /* number of non-empty write buffers */
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int transmitting;
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spinlock_t write_lock;
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struct mutex mutex;
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bool disconnected;
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struct usb_ch343_line_coding line; /* bits, stop, parity */
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struct work_struct work; /* work queue entry for line discipline waking up */
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unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */
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unsigned int ctrlout; /* output control lines (DTR, RTS) */
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struct async_icount iocount; /* counters for control line changes */
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struct async_icount oldcount; /* for comparison of counter */
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wait_queue_head_t wioctl; /* for ioctl */
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unsigned int writesize; /* max packet size for the output bulk endpoint */
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unsigned int readsize, ctrlsize; /* buffer sizes for freeing */
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unsigned int minor; /* ch343 minor number */
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unsigned char clocal; /* termios CLOCAL */
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unsigned int susp_count; /* number of suspended interfaces */
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u8 bInterval;
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struct usb_anchor delayed; /* writes queued for a device about to be woken */
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unsigned long quirks;
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u8 iface;
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CHIPTYPE chiptype;
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u16 idVendor;
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u16 idProduct;
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u8 gpio5dir;
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};
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#define CDC_DATA_INTERFACE_TYPE 0x0a
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/* constants describing various quirks and errors */
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#define NO_UNION_NORMAL BIT(0)
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#define SINGLE_RX_URB BIT(1)
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#define NO_CAP_LINE BIT(2)
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#define NO_DATA_INTERFACE BIT(4)
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#define IGNORE_DEVICE BIT(5)
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#define QUIRK_CONTROL_LINE_STATE BIT(6)
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#define CLEAR_HALT_CONDITIONS BIT(7)
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#endif
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