/*
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* IOMMU API for ARM architected SMMU implementations.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) 2013 ARM Limited
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*
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* Author: Will Deacon <will.deacon@arm.com>
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*/
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#ifndef _ARM_SMMU_REGS_H
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#define _ARM_SMMU_REGS_H
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/* Configuration registers */
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#define ARM_SMMU_GR0_sCR0 0x0
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#define sCR0_CLIENTPD (1 << 0)
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#define sCR0_GFRE (1 << 1)
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#define sCR0_GFIE (1 << 2)
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#define sCR0_EXIDENABLE (1 << 3)
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#define sCR0_GCFGFRE (1 << 4)
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#define sCR0_GCFGFIE (1 << 5)
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#define sCR0_USFCFG (1 << 10)
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#define sCR0_VMIDPNE (1 << 11)
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#define sCR0_PTM (1 << 12)
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#define sCR0_FB (1 << 13)
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#define sCR0_VMID16EN (1 << 31)
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#define sCR0_BSU_SHIFT 14
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#define sCR0_BSU_MASK 0x3
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#define sCR0_SHCFG_SHIFT 22
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#define sCR0_SHCFG_MASK 0x3
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#define sCR0_SHCFG_NSH 3
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/* Auxiliary Configuration register */
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#define ARM_SMMU_GR0_sACR 0x10
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/* Identification registers */
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#define ARM_SMMU_GR0_ID0 0x20
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#define ARM_SMMU_GR0_ID1 0x24
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#define ARM_SMMU_GR0_ID2 0x28
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#define ARM_SMMU_GR0_ID3 0x2c
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#define ARM_SMMU_GR0_ID4 0x30
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#define ARM_SMMU_GR0_ID5 0x34
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#define ARM_SMMU_GR0_ID6 0x38
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#define ARM_SMMU_GR0_ID7 0x3c
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#define ARM_SMMU_GR0_sGFSR 0x48
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#define ARM_SMMU_GR0_sGFSYNR0 0x50
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#define ARM_SMMU_GR0_sGFSYNR1 0x54
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#define ARM_SMMU_GR0_sGFSYNR2 0x58
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#define ID0_S1TS (1 << 30)
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#define ID0_S2TS (1 << 29)
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#define ID0_NTS (1 << 28)
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#define ID0_SMS (1 << 27)
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#define ID0_ATOSNS (1 << 26)
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#define ID0_PTFS_NO_AARCH32 (1 << 25)
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#define ID0_PTFS_NO_AARCH32S (1 << 24)
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#define ID0_CTTW (1 << 14)
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#define ID0_NUMIRPT_SHIFT 16
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#define ID0_NUMIRPT_MASK 0xff
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#define ID0_NUMSIDB_SHIFT 9
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#define ID0_NUMSIDB_MASK 0xf
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#define ID0_EXIDS (1 << 8)
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#define ID0_NUMSMRG_SHIFT 0
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#define ID0_NUMSMRG_MASK 0xff
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#define ID1_PAGESIZE (1 << 31)
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#define ID1_NUMPAGENDXB_SHIFT 28
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#define ID1_NUMPAGENDXB_MASK 7
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#define ID1_NUMS2CB_SHIFT 16
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#define ID1_NUMS2CB_MASK 0xff
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#define ID1_NUMCB_SHIFT 0
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#define ID1_NUMCB_MASK 0xff
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#define ID2_OAS_SHIFT 4
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#define ID2_OAS_MASK 0xf
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#define ID2_IAS_SHIFT 0
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#define ID2_IAS_MASK 0xf
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#define ID2_UBS_SHIFT 8
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#define ID2_UBS_MASK 0xf
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#define ID2_PTFS_4K (1 << 12)
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#define ID2_PTFS_16K (1 << 13)
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#define ID2_PTFS_64K (1 << 14)
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#define ID2_VMID16 (1 << 15)
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#define ID7_MAJOR_SHIFT 4
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#define ID7_MAJOR_MASK 0xf
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/* Global TLB invalidation */
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#define ARM_SMMU_GR0_TLBIVMID 0x64
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#define ARM_SMMU_GR0_TLBIALLNSNH 0x68
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#define ARM_SMMU_GR0_TLBIALLH 0x6c
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#define ARM_SMMU_GR0_sTLBGSYNC 0x70
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#define ARM_SMMU_GR0_sTLBGSTATUS 0x74
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#define sTLBGSTATUS_GSACTIVE (1 << 0)
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/* Stream mapping registers */
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#define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
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#define SMR_VALID (1 << 31)
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#define SMR_MASK_SHIFT 16
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#define SMR_MASK_MASK 0x7FFF
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#define SID_MASK 0x7FFF
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#define SMR_ID_SHIFT 0
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#define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
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#define S2CR_CBNDX_SHIFT 0
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#define S2CR_CBNDX_MASK 0xff
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#define S2CR_EXIDVALID (1 << 10)
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#define S2CR_TYPE_SHIFT 16
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#define S2CR_TYPE_MASK 0x3
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#define S2CR_SHCFG_SHIFT 8
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#define S2CR_SHCFG_MASK 0x3
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#define S2CR_SHCFG_NSH 0x3
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enum arm_smmu_s2cr_type {
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S2CR_TYPE_TRANS,
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S2CR_TYPE_BYPASS,
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S2CR_TYPE_FAULT,
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};
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#define S2CR_PRIVCFG_SHIFT 24
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#define S2CR_PRIVCFG_MASK 0x3
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enum arm_smmu_s2cr_privcfg {
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S2CR_PRIVCFG_DEFAULT,
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S2CR_PRIVCFG_DIPAN,
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S2CR_PRIVCFG_UNPRIV,
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S2CR_PRIVCFG_PRIV,
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};
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/* Context bank attribute registers */
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#define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
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#define CBAR_VMID_SHIFT 0
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#define CBAR_VMID_MASK 0xff
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#define CBAR_S1_BPSHCFG_SHIFT 8
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#define CBAR_S1_BPSHCFG_MASK 3
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#define CBAR_S1_BPSHCFG_NSH 3
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#define CBAR_S1_MEMATTR_SHIFT 12
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#define CBAR_S1_MEMATTR_MASK 0xf
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#define CBAR_S1_MEMATTR_WB 0xf
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#define CBAR_TYPE_SHIFT 16
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#define CBAR_TYPE_MASK 0x3
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#define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
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#define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
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#define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
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#define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
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#define CBAR_IRPTNDX_SHIFT 24
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#define CBAR_IRPTNDX_MASK 0xff
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#define ARM_SMMU_GR1_CBFRSYNRA(n) (0x400 + ((n) << 2))
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#define CBFRSYNRA_SID_MASK (0xffff)
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#define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
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#define CBA2R_RW64_32BIT (0 << 0)
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#define CBA2R_RW64_64BIT (1 << 0)
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#define CBA2R_VMID_SHIFT 16
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#define CBA2R_VMID_MASK 0xffff
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#define ARM_SMMU_CB_SCTLR 0x0
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#define ARM_SMMU_CB_ACTLR 0x4
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#define ARM_SMMU_CB_RESUME 0x8
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#define ARM_SMMU_CB_TTBCR2 0x10
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#define ARM_SMMU_CB_TTBR0 0x20
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#define ARM_SMMU_CB_TTBR1 0x28
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#define ARM_SMMU_CB_TTBCR 0x30
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#define ARM_SMMU_CB_CONTEXTIDR 0x34
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#define ARM_SMMU_CB_S1_MAIR0 0x38
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#define ARM_SMMU_CB_S1_MAIR1 0x3c
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#define ARM_SMMU_CB_PAR 0x50
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#define ARM_SMMU_CB_FSR 0x58
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#define ARM_SMMU_CB_FSRRESTORE 0x5c
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#define ARM_SMMU_CB_FAR 0x60
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#define ARM_SMMU_CB_FSYNR0 0x68
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#define ARM_SMMU_CB_FSYNR1 0x6c
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#define ARM_SMMU_CB_S1_TLBIVA 0x600
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#define ARM_SMMU_CB_S1_TLBIASID 0x610
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#define ARM_SMMU_CB_S1_TLBIALL 0x618
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#define ARM_SMMU_CB_S1_TLBIVAL 0x620
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#define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
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#define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
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#define ARM_SMMU_CB_TLBSYNC 0x7f0
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#define ARM_SMMU_CB_TLBSTATUS 0x7f4
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#define TLBSTATUS_SACTIVE (1 << 0)
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#define ARM_SMMU_CB_ATS1PR 0x800
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#define ARM_SMMU_CB_ATSR 0x8f0
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#define ARM_SMMU_STATS_SYNC_INV_TBU_ACK 0x25dc
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#define TBU_SYNC_ACK_MASK 0x1ff
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#define TBU_SYNC_ACK_SHIFT 17
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#define TBU_SYNC_REQ_MASK 0x1
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#define TBU_SYNC_REQ_SHIFT 16
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#define TBU_INV_ACK_MASK 0x1ff
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#define TBU_INV_ACK_SHIFT 1
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#define TBU_INV_REQ_MASK 0x1
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#define TBU_INV_REQ_SHIFT 0
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#define ARM_SMMU_TBU_PWR_STATUS 0x2204
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#define ARM_SMMU_MMU2QSS_AND_SAFE_WAIT_CNTR 0x2670
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#define TCU_SYNC_IN_PRGSS_MASK 0x1
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#define TCU_SYNC_IN_PRGSS_SHIFT 20
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#define TCU_INV_IN_PRGSS_MASK 0x1
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#define TCU_INV_IN_PRGSS_SHIFT 16
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#define TBUID_SHIFT 10
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#define SCTLR_MEM_ATTR_SHIFT 16
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#define SCTLR_SHCFG_SHIFT 22
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#define SCTLR_RACFG_SHIFT 24
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#define SCTLR_WACFG_SHIFT 26
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#define SCTLR_SHCFG_MASK 0x3
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#define SCTLR_SHCFG_NSH 0x3
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#define SCTLR_RACFG_RA 0x2
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#define SCTLR_WACFG_WA 0x2
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#define SCTLR_MEM_ATTR_OISH_WB_CACHE 0xf
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#define SCTLR_MTCFG (1 << 20)
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#define SCTLR_S1_ASIDPNE (1 << 12)
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#define SCTLR_CFCFG (1 << 7)
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#define SCTLR_HUPCF (1 << 8)
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#define SCTLR_CFIE (1 << 6)
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#define SCTLR_CFRE (1 << 5)
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#define SCTLR_E (1 << 4)
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#define SCTLR_AFE (1 << 2)
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#define SCTLR_TRE (1 << 1)
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#define SCTLR_M (1 << 0)
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#define CB_PAR_F (1 << 0)
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#define ATSR_ACTIVE (1 << 0)
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#define RESUME_RETRY (0 << 0)
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#define RESUME_TERMINATE (1 << 0)
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#define TTBCR2_SEP_SHIFT 15
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#define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
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#define TTBCR2_AS (1 << 4)
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#define TTBRn_ASID_SHIFT 48
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#define FSR_MULTI (1 << 31)
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#define FSR_SS (1 << 30)
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#define FSR_UUT (1 << 8)
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#define FSR_ASF (1 << 7)
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#define FSR_TLBLKF (1 << 6)
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#define FSR_TLBMCF (1 << 5)
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#define FSR_EF (1 << 4)
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#define FSR_PF (1 << 3)
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#define FSR_AFF (1 << 2)
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#define FSR_TF (1 << 1)
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#define FSR_IGN (FSR_AFF | FSR_ASF | \
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FSR_TLBMCF | FSR_TLBLKF)
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#define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
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FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
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#define FSYNR0_WNR (1 << 4)
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#define IMPL_DEF1_MICRO_MMU_CTRL 0
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#define MICRO_MMU_CTRL_LOCAL_HALT_REQ (1 << 2)
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#define MICRO_MMU_CTRL_IDLE (1 << 3)
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/* Definitions for implementation-defined registers */
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#define ACTLR_QCOM_OSH_SHIFT 28
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#define ACTLR_QCOM_OSH 1
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#define ACTLR_QCOM_ISH_SHIFT 29
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#define ACTLR_QCOM_ISH 1
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#define ACTLR_QCOM_NSH_SHIFT 30
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#define ACTLR_QCOM_NSH 1
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#endif /* _ARM_SMMU_REGS_H */
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