/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*/
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#ifndef __CLKC_H
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#define __CLKC_H
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#include <linux/clk-provider.h>
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#include "clk-regmap.h"
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#define PMASK(width) GENMASK(width - 1, 0)
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#define SETPMASK(width, shift) GENMASK(shift + width - 1, shift)
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#define CLRPMASK(width, shift) (~SETPMASK(width, shift))
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#define PARM_GET(width, shift, reg) \
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(((reg) & SETPMASK(width, shift)) >> (shift))
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#define PARM_SET(width, shift, reg, val) \
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(((reg) & CLRPMASK(width, shift)) | ((val) << (shift)))
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#define MESON_PARM_APPLICABLE(p) (!!((p)->width))
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struct parm {
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u16 reg_off;
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u8 shift;
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u8 width;
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};
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static inline unsigned int meson_parm_read(struct regmap *map, struct parm *p)
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{
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unsigned int val;
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regmap_read(map, p->reg_off, &val);
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return PARM_GET(p->width, p->shift, val);
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}
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static inline void meson_parm_write(struct regmap *map, struct parm *p,
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unsigned int val)
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{
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regmap_update_bits(map, p->reg_off, SETPMASK(p->width, p->shift),
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val << p->shift);
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}
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struct pll_rate_table {
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unsigned long rate;
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u16 m;
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u16 n;
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u16 od;
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u16 od2;
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u16 od3;
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};
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#define PLL_RATE(_r, _m, _n, _od) \
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{ \
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.rate = (_r), \
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.m = (_m), \
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.n = (_n), \
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.od = (_od), \
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}
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#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
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struct meson_clk_pll_data {
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struct parm m;
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struct parm n;
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struct parm frac;
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struct parm od;
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struct parm od2;
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struct parm od3;
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struct parm l;
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struct parm rst;
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const struct reg_sequence *init_regs;
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unsigned int init_count;
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const struct pll_rate_table *table;
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u8 flags;
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};
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#define to_meson_clk_pll(_hw) container_of(_hw, struct meson_clk_pll, hw)
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struct meson_clk_mpll_data {
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struct parm sdm;
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struct parm sdm_en;
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struct parm n2;
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struct parm ssen;
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struct parm misc;
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spinlock_t *lock;
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u8 flags;
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};
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#define CLK_MESON_MPLL_ROUND_CLOSEST BIT(0)
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struct meson_clk_phase_data {
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struct parm ph;
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};
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int meson_clk_degrees_from_val(unsigned int val, unsigned int width);
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unsigned int meson_clk_degrees_to_val(int degrees, unsigned int width);
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#define MESON_GATE(_name, _reg, _bit) \
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struct clk_regmap _name = { \
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.data = &(struct clk_regmap_gate_data){ \
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.offset = (_reg), \
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.bit_idx = (_bit), \
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}, \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name, \
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.ops = &clk_regmap_gate_ops, \
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.parent_names = (const char *[]){ "clk81" }, \
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.num_parents = 1, \
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.flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \
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}, \
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};
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/* clk_ops */
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extern const struct clk_ops meson_clk_pll_ro_ops;
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extern const struct clk_ops meson_clk_pll_ops;
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extern const struct clk_ops meson_clk_cpu_ops;
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extern const struct clk_ops meson_clk_mpll_ro_ops;
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extern const struct clk_ops meson_clk_mpll_ops;
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extern const struct clk_ops meson_clk_phase_ops;
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#endif /* __CLKC_H */
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