/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
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/*
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* Copyright (c) 2017 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* Copyright (c) 2018 Amlogic, inc.
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* Author: Qiufang Dai <qiufang.dai@amlogic.com>
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*/
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#ifndef __AXG_AOCLKC_H
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#define __AXG_AOCLKC_H
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#define NR_CLKS 11
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/* AO Configuration Clock registers offsets
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* Register offsets from the data sheet must be multiplied by 4.
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*/
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#define AO_RTI_PWR_CNTL_REG1 0x0C
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#define AO_RTI_PWR_CNTL_REG0 0x10
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#define AO_RTI_GEN_CNTL_REG0 0x40
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#define AO_OSCIN_CNTL 0x58
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#define AO_CRT_CLK_CNTL1 0x68
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#define AO_SAR_CLK 0x90
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#define AO_RTC_ALT_CLK_CNTL0 0x94
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#define AO_RTC_ALT_CLK_CNTL1 0x98
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#include <dt-bindings/clock/axg-aoclkc.h>
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#include <dt-bindings/reset/axg-aoclkc.h>
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#endif /* __AXG_AOCLKC_H */
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