* rk3368 dram default timing is at arch/arm64/boot/dts/rk3368_dram_default_timing.dtsi
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Required properties:
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- compatible : Should be "rockchip,ddr-timing"
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- dram_spd_bin : value is defined at include/dt-bindings/clock/ddr.h
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it select ddr3 cl-trp-trcd type, default value "DDR3_DEFAULT".it must selected
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according to "Speed Bin" in ddr3 datasheet, DO NOT use smaller "Speed Bin" than
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ddr3 exactly is.
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- sr_idle : configure the SR_IDLE value, defined the selfrefresh idle period,
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memories are places into self-refresh mode if bus is idle for SR_IDLE*32 DFI
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clocks (DFI clocks freq is half of dram's clocks), defaule value is "1"
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- pd_idle : config the PD_IDLE value, defined the power-down idle period, memories
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are places into power-down mode if bus is idle for PD_IDLE DFI clocks.
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- dram_dll_disb_freq : it's defined the DDR3 dll bypass frequency in MHz (Mega Hz),
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when ddr freq less than DRAM_DLL_DISB_FREQ, ddr3 dll will bypssed
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note: if dll was bypassed, the odt also stop working.
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- phy_dll_disb_freq : defined the PHY dll bypass frequency in MHz (Mega Hz),
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when ddr freq less than DRAM_DLL_DISB_FREQ, phy dll will bypssed
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note: phy dll and phy odt are independent
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- dram_odt_disb_freq : defined the DDR3 and LPDDR3 odt disable frequency in
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MHz (Mega Hz), when ddr frequency less then DRAM_ODT_DISB_FREQ, the DDR3
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and LPDDR3 ODT are disabled.
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- phy_odt_disb_freq : defined the PHY odt disable frequency in MHz (Mega Hz),
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when ddr frequency less then PHY_ODT_DISB_FREQ, the PHY ODT are disabled.
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- ddr3_drv : define the DDR3 driver stength in ohm, default value is DDR3_DS_40
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- ddr3_odt : define the DDR3 ODT in ohm, default value is DDR3_ODT_120
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- lpddr3_drv : define the lPDDR3 driver stength in ohm, default value is LP3_DS_34
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- lpddr3_odt : define the LPDDR3 ODT in ohm, default value is LP3_ODT_240
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- lpddr2_drv : define the LPDDR2 driver stength in ohm, default value is LP2_DS_34
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- phy_clk_drv : define the phy clocks driver strength in ohm, default value is
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PHY_RON_45ohm
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- phy_cmd_drv : define the phy commands driver strength in ohm, default value is
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PHY_RON_34ohm
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- phy_dqs_drv : define the phy dqs and dq driver strength in ohm, default value is
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PHY_RON_34ohm
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- phy_odt : define the phy odt in ohm, default value isPHY_RTT_279ohm
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- ddr_2t : define the uptcl CMD/CLK 2T mode, default value is ENABLE_DDR_2T.
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the driver strength and odt value are defined at include/dt-bindings/dram/rockchip,rk3368.h
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Example:
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/ {
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ddr_timing: ddr_timing {
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compatible = "rockchip,ddr-timing";
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dram_spd_bin = <DDR3_DEFAULT>;
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sr_idle = <1>;
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pd_idle = <0x20>;
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dram_dll_disb_freq = <300>;
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phy_dll_disb_freq = <400>;
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dram_odt_disb_freq = <333>;
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phy_odt_disb_freq = <333>;
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ddr3_drv = <DDR3_DS_40ohm>;
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ddr3_odt = <DDR3_ODT_120ohm>;
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lpddr3_drv = <LP3_DS_34ohm>;
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lpddr3_odt = <LP3_ODT_240ohm>;
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lpddr2_drv = <LP2_DS_34ohm>;/*lpddr2 not supported odt*/
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phy_clk_drv = <PHY_RON_45ohm>;
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phy_cmd_drv = <PHY_RON_34ohm>;
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phy_dqs_drv = <PHY_RON_34ohm>;
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phy_odt = <PHY_RTT_279ohm>;
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ddr_2t = <ENABLE_DDR_2T>;
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};
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};
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