/*------------------------------------------------------------------------------
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-- --
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-- This software is confidential and proprietary and may be used --
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-- only as expressly authorized by a licensing agreement from --
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-- --
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-- Rockchip Products . --
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-- --
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-- (C) COPYRIGHT 2014 ROCKCHIP PRODUCTS --
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-- ALL RIGHTS RESERVED --
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-- --
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-- The entire notice above must be reproduced --
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-- on all copies and should not be removed. --
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-- --
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--------------------------------------------------------------------------------
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--
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-- Description : Hardware PP system configuration
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--
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--------------------------------------------------------------------------------
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--
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--
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--
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------------------------------------------------------------------------------*/
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#ifndef __PPCFG_H__
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#define __PPCFG_H__
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/* predefined values of HW system parameters. DO NOT ALTER! */
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#define PP_RK70_PICTURE_LITTLE_ENDIAN 1
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#define PP_RK70_PICTURE_BIG_ENDIAN 0
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#define PP_RK70_BUS_BURST_LENGTH_UNDEFINED 0
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#define PP_RK70_BUS_BURST_LENGTH_4 4
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#define PP_RK70_BUS_BURST_LENGTH_8 8
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#define PP_RK70_BUS_BURST_LENGTH_16 16
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#define PP_RK70_DATA_BUS_WIDTH_32 4
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#define PP_RK70_DATA_BUS_WIDTH_64 8
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/* end of predefined values */
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/* now what we use */
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#ifndef PP_RK70_USING_IRQ
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/* use the HW IRQ or not; set to non-zero to enable */
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/* if set to zero the software will disable the PP IRQ */
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/* generation in the control register */
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#define PP_RK70_USING_IRQ 1
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#endif
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#ifndef PP_RK70_SWAP_32_WORDS
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/* in 64 bit bus environment the 32 bit words can be swapped */
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#define PP_RK70_SWAP_32_WORDS 0
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#endif
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#ifndef PP_RK70_INPUT_PICTURE_ENDIAN
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/* this should match the system endianess, so that PP reads */
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/* the input pixel data in the right order */
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#define PP_RK70_INPUT_PICTURE_ENDIAN PP_RK70_PICTURE_LITTLE_ENDIAN
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#endif
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#ifndef PP_RK70_OUTPUT_PICTURE_ENDIAN
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/* this should match the system endianess, so that PP writes */
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/* the output pixel data in the right order */
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#define PP_RK70_OUTPUT_PICTURE_ENDIAN PP_RK70_PICTURE_LITTLE_ENDIAN
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#endif
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#ifndef PP_RK70_BUS_BURST_LENGTH
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/* how long are the hardware data bursts; better left unchanged */
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#define PP_RK70_BUS_BURST_LENGTH PP_RK70_BUS_BURST_LENGTH_16
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#endif
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#ifndef PP_RK70_DATA_BUS_WIDTH
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/* data bus width of the PP hardware; note that this might not be */
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/* the same with the CPU's data bus width */
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#define PP_RK70_DATA_BUS_WIDTH PP_RK70_DATA_BUS_WIDTH_32
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#endif
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#ifndef PP_RK70_LATENCY_COMPENSATION
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/* compensation for bus latency; values up to 63 */
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#define PP_RK70_LATENCY_COMPENSATION 0
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#endif
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#ifndef PP_RK70_INTERNAL_CLOCK_GATING
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/* clock is gated from PP structures that are not used */
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#define PP_RK70_INTERNAL_CLOCK_GATING 0
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#endif
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#ifndef PP_RK70_DATA_DISCARD_ENABLE
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#define PP_RK70_DATA_DISCARD_ENABLE 0
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#endif
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#ifndef PP_RK70_SWAP_32_WORDS_INPUT
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#define PP_RK70_SWAP_32_WORDS_INPUT 0
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#endif
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/* AXI bus read and write ID values used by HW. 0 - 255 */
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#ifndef PP_RK70_AXI_ID_R
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#define PP_RK70_AXI_ID_R 0
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#endif
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#ifndef PP_RK70_AXI_ID_W
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#define PP_RK70_AXI_ID_W 0
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#endif
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/* AXI single command multiple data disable not set */
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#define PP_RK70_SCMD_DISABLE 0
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/* flag to ignore endianness when reading RGB format alpha blend picture.
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* DO NOT ALTER! */
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#define PP_RK70_IGNORE_ABLEND_ENDIANNESS 0
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#endif /* __PPCFG_H__ */
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