/*------------------------------------------------------------------------------
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-- --
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-- This software is confidential and proprietary and may be used --
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-- only as expressly authorized by a licensing agreement from --
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-- --
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-- Rockchip Products . --
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-- --
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-- (C) COPYRIGHT 2014 ROCKCHIP PRODUCTS --
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-- ALL RIGHTS RESERVED --
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-- --
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-- The entire notice above must be reproduced --
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-- on all copies and should not be removed. --
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-- --
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--------------------------------------------------------------------------------
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--
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-- Description : Hardware decoder system configuration
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--
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--------------------------------------------------------------------------------
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--
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--
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--
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------------------------------------------------------------------------------*/
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#ifndef __DEC_RK70_CFG_H__
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#define __DEC_RK70_CFG_H__
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/* predefined values of HW system parameters. DO NOT ALTER! */
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#define DEC_RK70_LITTLE_ENDIAN 1
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#define DEC_RK70_BIG_ENDIAN 0
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#define DEC_RK70_BUS_BURST_LENGTH_UNDEFINED 0
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#define DEC_RK70_BUS_BURST_LENGTH_4 4
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#define DEC_RK70_BUS_BURST_LENGTH_8 8
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#define DEC_RK70_BUS_BURST_LENGTH_16 16
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#define DEC_RK70_ASIC_SERVICE_PRIORITY_DEFAULT 0
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#define DEC_RK70_ASIC_SERVICE_PRIORITY_WR_1 1
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#define DEC_RK70_ASIC_SERVICE_PRIORITY_WR_2 2
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#define DEC_RK70_ASIC_SERVICE_PRIORITY_RD_1 3
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#define DEC_RK70_ASIC_SERVICE_PRIORITY_RD_2 4
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#define DEC_RK70_OUTPUT_FORMAT_RASTER_SCAN 0
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#define DEC_RK70_OUTPUT_FORMAT_TILED 1
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/* end of predefined values */
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/* now what we use */
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#ifndef DEC_RK70_USING_IRQ
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/* Control IRQ generation by decoder hardware */
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#define DEC_RK70_USING_IRQ 1
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#endif
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#ifndef DEC_RK70_ASIC_SERVICE_PRIORITY
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/* hardware intgernal prioriy scheme. better left unchanged */
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#define DEC_RK70_ASIC_SERVICE_PRIORITY DEC_RK70_ASIC_SERVICE_PRIORITY_DEFAULT
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#endif
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/* AXI single command multiple data disable not set */
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#define DEC_RK70_SCMD_DISABLE 0
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/* Advanced prefetch disable flag. If disable flag is set, product shall
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* operate akin to 9190 and earlier products. */
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#define DEC_RK70_APF_DISABLE 0
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#ifndef DEC_RK70_BUS_BURST_LENGTH
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/* how long are the hardware data bursts; better left unchanged */
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#define DEC_RK70_BUS_BURST_LENGTH DEC_RK70_BUS_BURST_LENGTH_16
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#endif
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#ifndef DEC_RK70_INPUT_STREAM_ENDIAN
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/* this should match the system endianess, so that Decoder reads */
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/* the input stream in the right order */
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#define DEC_RK70_INPUT_STREAM_ENDIAN DEC_RK70_LITTLE_ENDIAN
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#endif
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#ifndef DEC_RK70_OUTPUT_PICTURE_ENDIAN
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/* this should match the system endianess, so that Decoder writes */
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/* the output pixel data in the right order */
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#define DEC_RK70_OUTPUT_PICTURE_ENDIAN DEC_RK70_LITTLE_ENDIAN
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#endif
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#ifndef DEC_RK70_LATENCY_COMPENSATION
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/* compensation for bus latency; values up to 63 */
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#define DEC_RK70_LATENCY_COMPENSATION 0
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#endif
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#ifndef DEC_RK70_INTERNAL_CLOCK_GATING
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/* clock is gated from decoder structures that are not used */
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#define DEC_RK70_INTERNAL_CLOCK_GATING 1
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#endif
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#ifndef DEC_RK70_OUTPUT_FORMAT
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/* Decoder output picture format in external memory: Raster-scan or */
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/*macroblock tiled i.e. macroblock data written in consecutive addresses */
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#define DEC_RK70_OUTPUT_FORMAT DEC_RK70_OUTPUT_FORMAT_RASTER_SCAN
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#endif
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#ifndef DEC_RK70_DATA_DISCARD_ENABLE
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#define DEC_RK70_DATA_DISCARD_ENABLE 0
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#endif
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/* Decoder output data swap for 32bit words*/
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#ifndef DEC_RK70_OUTPUT_SWAP_32_ENABLE
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#define DEC_RK70_OUTPUT_SWAP_32_ENABLE 1
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#endif
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/* Decoder input data swap(excluding stream data) for 32bit words*/
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#ifndef DEC_RK70_INPUT_DATA_SWAP_32_ENABLE
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#define DEC_RK70_INPUT_DATA_SWAP_32_ENABLE 1
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#endif
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/* Decoder input stream swap for 32bit words */
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#ifndef DEC_RK70_INPUT_STREAM_SWAP_32_ENABLE
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#define DEC_RK70_INPUT_STREAM_SWAP_32_ENABLE 1
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#endif
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/* Decoder input data endian. Do not modify this! */
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#ifndef DEC_RK70_INPUT_DATA_ENDIAN
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#define DEC_RK70_INPUT_DATA_ENDIAN DEC_RK70_BIG_ENDIAN
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#endif
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/* AXI bus read and write ID values used by HW. 0 - 255 */
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#ifndef DEC_RK70_AXI_ID_R
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#define DEC_RK70_AXI_ID_R 0xff
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#endif
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#ifndef DEC_RK70_AXI_ID_W
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#define DEC_RK70_AXI_ID_W 0
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#endif
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/* Check validity of values */
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/* data discard and tiled mode can not be on simultaneously */
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#if (DEC_RK70_DATA_DISCARD_ENABLE && (DEC_RK70_OUTPUT_FORMAT == DEC_RK70_OUTPUT_FORMAT_TILED))
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#error "Bad value specified: DEC_RK70_DATA_DISCARD_ENABLE && (DEC_RK70_OUTPUT_FORMAT == DEC_RK70_OUTPUT_FORMAT_TILED)"
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#endif
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#if (DEC_RK70_OUTPUT_PICTURE_ENDIAN > 1)
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#error "Bad value specified for DEC_RK70_OUTPUT_PICTURE_ENDIAN"
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#endif
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#if (DEC_RK70_OUTPUT_FORMAT > 1)
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#error "Bad value specified for DEC_RK70_OUTPUT_FORMAT"
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#endif
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#if (DEC_RK70_BUS_BURST_LENGTH > 31)
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#error "Bad value specified for DEC_RK70_AMBA_BURST_LENGTH"
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#endif
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#if (DEC_RK70_ASIC_SERVICE_PRIORITY > 4)
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#error "Bad value specified for DEC_RK70_ASIC_SERVICE_PRIORITY"
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#endif
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#if (DEC_RK70_LATENCY_COMPENSATION > 63)
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#error "Bad value specified for DEC_RK70_LATENCY_COMPENSATION"
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#endif
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#if (DEC_RK70_OUTPUT_SWAP_32_ENABLE > 1)
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#error "Bad value specified for DEC_RK70_OUTPUT_SWAP_32_ENABLE"
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#endif
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#if (DEC_RK70_INPUT_DATA_SWAP_32_ENABLE > 1)
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#error "Bad value specified for DEC_RK70_INPUT_DATA_SWAP_32_ENABLE"
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#endif
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#if (DEC_RK70_INPUT_STREAM_SWAP_32_ENABLE > 1)
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#error "Bad value specified for DEC_RK70_INPUT_STREAM_SWAP_32_ENABLE"
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#endif
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#if (DEC_RK70_OUTPUT_SWAP_32_ENABLE > 1)
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#error "Bad value specified for DEC_RK70_INPUT_DATA_ENDIAN"
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#endif
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#if (DEC_RK70_DATA_DISCARD_ENABLE > 1)
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#error "Bad value specified for DEC_RK70_DATA_DISCARD_ENABLE"
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#endif
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/* Common defines for the decoder */
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/* Number registers for the decoder */
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#define DEC_RK70_REGISTERS 159
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/* Max amount of stream */
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#define DEC_RK70_MAX_STREAM ((1<<24)-1)
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/* Timeout value for the VPUWaitHwReady() call. */
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/* Set to -1 for an unspecified value */
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#ifndef DEC_RK70_TIMEOUT_LENGTH
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#define DEC_RK70_TIMEOUT_LENGTH -1
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#endif
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/* Enable HW internal watchdog timeout IRQ */
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#define DEC_RK70_HW_TIMEOUT_INT_ENA 1
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/* Memory wait states for reference buffer */
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#define DEC_RK70_REFBU_WIDTH 64
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#define DEC_RK70_REFBU_LATENCY 20
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#define DEC_RK70_REFBU_NONSEQ 8
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#define DEC_RK70_REFBU_SEQ 1
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#define DEC_SET_APF_THRESHOLD(reghandle) \
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{ \
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u32 apfTmpThreshold = 0; \
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rk_SetRegisterFile(reghandle, HWIF_DEC_ADV_PRE_DIS, DEC_RK70_APF_DISABLE ); \
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if((DEC_RK70_APF_DISABLE) == 0) \
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{ \
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if(DEC_RK70_REFBU_SEQ) \
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apfTmpThreshold = DEC_RK70_REFBU_NONSEQ/DEC_RK70_REFBU_SEQ; \
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else \
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apfTmpThreshold = DEC_RK70_REFBU_NONSEQ; \
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if( apfTmpThreshold > 63 ) \
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apfTmpThreshold = 63; \
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} \
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rk_SetRegisterFile(reghandle, HWIF_APF_THRESHOLD, apfTmpThreshold ); \
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}
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/* Check validity of the stream addresses */
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#define RK70_CHECK_BUS_ADDRESS(d) ((d) < 64 ? 1 : 0)
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#define RK70_CHECK_VIRTUAL_ADDRESS(d) (((void*)(d) < (void*)64) ? 1 : 0)
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#endif /* __DEC_RK70_CFG_H__ */
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