/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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*
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* (C) COPYRIGHT 2021 ARM Limited. All rights reserved.
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*
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* This program is free software and is provided to you under the terms of the
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* GNU General Public License version 2 as published by the Free Software
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* Foundation, and any use by you of this program is subject to the terms
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* of such GNU license.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you can access it online at
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* http://www.gnu.org/licenses/gpl-2.0.html.
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*
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*/
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#ifndef _UAPI_KBASE_GPU_REGMAP_H_
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#define _UAPI_KBASE_GPU_REGMAP_H_
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#include "mali_kbase_gpu_coherency.h"
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#include "mali_kbase_gpu_id.h"
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#if MALI_USE_CSF
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#include "backend/mali_kbase_gpu_regmap_csf.h"
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#else
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#include "backend/mali_kbase_gpu_regmap_jm.h"
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#endif
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/* Begin Register Offsets */
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/* GPU control registers */
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#define GPU_CONTROL_BASE 0x0000
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#define GPU_CONTROL_REG(r) (GPU_CONTROL_BASE + (r))
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#define GPU_ID 0x000 /* (RO) GPU and revision identifier */
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#define L2_FEATURES 0x004 /* (RO) Level 2 cache features */
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#define TILER_FEATURES 0x00C /* (RO) Tiler Features */
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#define MEM_FEATURES 0x010 /* (RO) Memory system features */
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#define MMU_FEATURES 0x014 /* (RO) MMU features */
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#define AS_PRESENT 0x018 /* (RO) Address space slots present */
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#define GPU_IRQ_RAWSTAT 0x020 /* (RW) */
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#define GPU_IRQ_CLEAR 0x024 /* (WO) */
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#define GPU_IRQ_MASK 0x028 /* (RW) */
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#define GPU_IRQ_STATUS 0x02C /* (RO) */
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#define GPU_COMMAND 0x030 /* (WO) */
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#define GPU_STATUS 0x034 /* (RO) */
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#define GPU_DBGEN (1 << 8) /* DBGEN wire status */
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#define GPU_FAULTSTATUS 0x03C /* (RO) GPU exception type and fault status */
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#define GPU_FAULTADDRESS_LO 0x040 /* (RO) GPU exception fault address, low word */
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#define GPU_FAULTADDRESS_HI 0x044 /* (RO) GPU exception fault address, high word */
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#define L2_CONFIG 0x048 /* (RW) Level 2 cache configuration */
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#define GROUPS_L2_COHERENT (1 << 0) /* Cores groups are l2 coherent */
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#define SUPER_L2_COHERENT (1 << 1) /* Shader cores within a core
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* supergroup are l2 coherent
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*/
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#define PWR_KEY 0x050 /* (WO) Power manager key register */
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#define PWR_OVERRIDE0 0x054 /* (RW) Power manager override settings */
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#define PWR_OVERRIDE1 0x058 /* (RW) Power manager override settings */
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#define GPU_FEATURES_LO 0x060 /* (RO) GPU features, low word */
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#define GPU_FEATURES_HI 0x064 /* (RO) GPU features, high word */
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#define PRFCNT_FEATURES 0x068 /* (RO) Performance counter features */
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#define TIMESTAMP_OFFSET_LO 0x088 /* (RW) Global time stamp offset, low word */
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#define TIMESTAMP_OFFSET_HI 0x08C /* (RW) Global time stamp offset, high word */
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#define CYCLE_COUNT_LO 0x090 /* (RO) Cycle counter, low word */
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#define CYCLE_COUNT_HI 0x094 /* (RO) Cycle counter, high word */
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#define TIMESTAMP_LO 0x098 /* (RO) Global time stamp counter, low word */
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#define TIMESTAMP_HI 0x09C /* (RO) Global time stamp counter, high word */
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#define THREAD_MAX_THREADS 0x0A0 /* (RO) Maximum number of threads per core */
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#define THREAD_MAX_WORKGROUP_SIZE 0x0A4 /* (RO) Maximum workgroup size */
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#define THREAD_MAX_BARRIER_SIZE 0x0A8 /* (RO) Maximum threads waiting at a barrier */
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#define THREAD_FEATURES 0x0AC /* (RO) Thread features */
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#define THREAD_TLS_ALLOC 0x310 /* (RO) Number of threads per core that TLS must be allocated for */
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#define TEXTURE_FEATURES_0 0x0B0 /* (RO) Support flags for indexed texture formats 0..31 */
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#define TEXTURE_FEATURES_1 0x0B4 /* (RO) Support flags for indexed texture formats 32..63 */
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#define TEXTURE_FEATURES_2 0x0B8 /* (RO) Support flags for indexed texture formats 64..95 */
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#define TEXTURE_FEATURES_3 0x0BC /* (RO) Support flags for texture order */
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#define TEXTURE_FEATURES_REG(n) GPU_CONTROL_REG(TEXTURE_FEATURES_0 + ((n) << 2))
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#define SHADER_PRESENT_LO 0x100 /* (RO) Shader core present bitmap, low word */
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#define SHADER_PRESENT_HI 0x104 /* (RO) Shader core present bitmap, high word */
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#define TILER_PRESENT_LO 0x110 /* (RO) Tiler core present bitmap, low word */
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#define TILER_PRESENT_HI 0x114 /* (RO) Tiler core present bitmap, high word */
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#define L2_PRESENT_LO 0x120 /* (RO) Level 2 cache present bitmap, low word */
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#define L2_PRESENT_HI 0x124 /* (RO) Level 2 cache present bitmap, high word */
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#define STACK_PRESENT_LO 0xE00 /* (RO) Core stack present bitmap, low word */
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#define STACK_PRESENT_HI 0xE04 /* (RO) Core stack present bitmap, high word */
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#define SHADER_READY_LO 0x140 /* (RO) Shader core ready bitmap, low word */
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#define SHADER_READY_HI 0x144 /* (RO) Shader core ready bitmap, high word */
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#define TILER_READY_LO 0x150 /* (RO) Tiler core ready bitmap, low word */
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#define TILER_READY_HI 0x154 /* (RO) Tiler core ready bitmap, high word */
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#define L2_READY_LO 0x160 /* (RO) Level 2 cache ready bitmap, low word */
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#define L2_READY_HI 0x164 /* (RO) Level 2 cache ready bitmap, high word */
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#define STACK_READY_LO 0xE10 /* (RO) Core stack ready bitmap, low word */
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#define STACK_READY_HI 0xE14 /* (RO) Core stack ready bitmap, high word */
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#define SHADER_PWRON_LO 0x180 /* (WO) Shader core power on bitmap, low word */
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#define SHADER_PWRON_HI 0x184 /* (WO) Shader core power on bitmap, high word */
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#define TILER_PWRON_LO 0x190 /* (WO) Tiler core power on bitmap, low word */
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#define TILER_PWRON_HI 0x194 /* (WO) Tiler core power on bitmap, high word */
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#define L2_PWRON_LO 0x1A0 /* (WO) Level 2 cache power on bitmap, low word */
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#define L2_PWRON_HI 0x1A4 /* (WO) Level 2 cache power on bitmap, high word */
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#define STACK_PWRON_LO 0xE20 /* (RO) Core stack power on bitmap, low word */
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#define STACK_PWRON_HI 0xE24 /* (RO) Core stack power on bitmap, high word */
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#define SHADER_PWROFF_LO 0x1C0 /* (WO) Shader core power off bitmap, low word */
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#define SHADER_PWROFF_HI 0x1C4 /* (WO) Shader core power off bitmap, high word */
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#define TILER_PWROFF_LO 0x1D0 /* (WO) Tiler core power off bitmap, low word */
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#define TILER_PWROFF_HI 0x1D4 /* (WO) Tiler core power off bitmap, high word */
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#define L2_PWROFF_LO 0x1E0 /* (WO) Level 2 cache power off bitmap, low word */
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#define L2_PWROFF_HI 0x1E4 /* (WO) Level 2 cache power off bitmap, high word */
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#define STACK_PWROFF_LO 0xE30 /* (RO) Core stack power off bitmap, low word */
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#define STACK_PWROFF_HI 0xE34 /* (RO) Core stack power off bitmap, high word */
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#define SHADER_PWRTRANS_LO 0x200 /* (RO) Shader core power transition bitmap, low word */
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#define SHADER_PWRTRANS_HI 0x204 /* (RO) Shader core power transition bitmap, high word */
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#define TILER_PWRTRANS_LO 0x210 /* (RO) Tiler core power transition bitmap, low word */
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#define TILER_PWRTRANS_HI 0x214 /* (RO) Tiler core power transition bitmap, high word */
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#define L2_PWRTRANS_LO 0x220 /* (RO) Level 2 cache power transition bitmap, low word */
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#define L2_PWRTRANS_HI 0x224 /* (RO) Level 2 cache power transition bitmap, high word */
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#define ASN_HASH_0 0x02C0 /* (RW) ASN hash function argument 0 */
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#define ASN_HASH(n) (ASN_HASH_0 + (n)*4)
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#define ASN_HASH_COUNT 3
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#define STACK_PWRTRANS_LO 0xE40 /* (RO) Core stack power transition bitmap, low word */
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#define STACK_PWRTRANS_HI 0xE44 /* (RO) Core stack power transition bitmap, high word */
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#define SHADER_PWRACTIVE_LO 0x240 /* (RO) Shader core active bitmap, low word */
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#define SHADER_PWRACTIVE_HI 0x244 /* (RO) Shader core active bitmap, high word */
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#define TILER_PWRACTIVE_LO 0x250 /* (RO) Tiler core active bitmap, low word */
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#define TILER_PWRACTIVE_HI 0x254 /* (RO) Tiler core active bitmap, high word */
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#define L2_PWRACTIVE_LO 0x260 /* (RO) Level 2 cache active bitmap, low word */
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#define L2_PWRACTIVE_HI 0x264 /* (RO) Level 2 cache active bitmap, high word */
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#define COHERENCY_FEATURES 0x300 /* (RO) Coherency features present */
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#define COHERENCY_ENABLE 0x304 /* (RW) Coherency enable */
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#define SHADER_CONFIG 0xF04 /* (RW) Shader core configuration (implementation-specific) */
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#define TILER_CONFIG 0xF08 /* (RW) Tiler core configuration (implementation-specific) */
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#define L2_MMU_CONFIG 0xF0C /* (RW) L2 cache and MMU configuration (implementation-specific) */
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/* Job control registers */
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#define JOB_CONTROL_BASE 0x1000
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#define JOB_CONTROL_REG(r) (JOB_CONTROL_BASE + (r))
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#define JOB_IRQ_RAWSTAT 0x000 /* Raw interrupt status register */
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#define JOB_IRQ_CLEAR 0x004 /* Interrupt clear register */
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#define JOB_IRQ_MASK 0x008 /* Interrupt mask register */
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#define JOB_IRQ_STATUS 0x00C /* Interrupt status register */
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/* MMU control registers */
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#define MEMORY_MANAGEMENT_BASE 0x2000
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#define MMU_REG(r) (MEMORY_MANAGEMENT_BASE + (r))
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#define MMU_IRQ_RAWSTAT 0x000 /* (RW) Raw interrupt status register */
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#define MMU_IRQ_CLEAR 0x004 /* (WO) Interrupt clear register */
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#define MMU_IRQ_MASK 0x008 /* (RW) Interrupt mask register */
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#define MMU_IRQ_STATUS 0x00C /* (RO) Interrupt status register */
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#define MMU_AS0 0x400 /* Configuration registers for address space 0 */
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#define MMU_AS1 0x440 /* Configuration registers for address space 1 */
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#define MMU_AS2 0x480 /* Configuration registers for address space 2 */
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#define MMU_AS3 0x4C0 /* Configuration registers for address space 3 */
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#define MMU_AS4 0x500 /* Configuration registers for address space 4 */
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#define MMU_AS5 0x540 /* Configuration registers for address space 5 */
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#define MMU_AS6 0x580 /* Configuration registers for address space 6 */
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#define MMU_AS7 0x5C0 /* Configuration registers for address space 7 */
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#define MMU_AS8 0x600 /* Configuration registers for address space 8 */
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#define MMU_AS9 0x640 /* Configuration registers for address space 9 */
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#define MMU_AS10 0x680 /* Configuration registers for address space 10 */
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#define MMU_AS11 0x6C0 /* Configuration registers for address space 11 */
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#define MMU_AS12 0x700 /* Configuration registers for address space 12 */
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#define MMU_AS13 0x740 /* Configuration registers for address space 13 */
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#define MMU_AS14 0x780 /* Configuration registers for address space 14 */
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#define MMU_AS15 0x7C0 /* Configuration registers for address space 15 */
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/* MMU address space control registers */
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#define MMU_AS_REG(n, r) (MMU_REG(MMU_AS0 + ((n) << 6)) + (r))
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#define AS_TRANSTAB_LO 0x00 /* (RW) Translation Table Base Address for address space n, low word */
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#define AS_TRANSTAB_HI 0x04 /* (RW) Translation Table Base Address for address space n, high word */
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#define AS_MEMATTR_LO 0x08 /* (RW) Memory attributes for address space n, low word. */
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#define AS_MEMATTR_HI 0x0C /* (RW) Memory attributes for address space n, high word. */
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#define AS_LOCKADDR_LO 0x10 /* (RW) Lock region address for address space n, low word */
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#define AS_LOCKADDR_HI 0x14 /* (RW) Lock region address for address space n, high word */
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#define AS_COMMAND 0x18 /* (WO) MMU command register for address space n */
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#define AS_FAULTSTATUS 0x1C /* (RO) MMU fault status register for address space n */
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#define AS_FAULTADDRESS_LO 0x20 /* (RO) Fault Address for address space n, low word */
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#define AS_FAULTADDRESS_HI 0x24 /* (RO) Fault Address for address space n, high word */
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#define AS_STATUS 0x28 /* (RO) Status flags for address space n */
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/* (RW) Translation table configuration for address space n, low word */
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#define AS_TRANSCFG_LO 0x30
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/* (RW) Translation table configuration for address space n, high word */
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#define AS_TRANSCFG_HI 0x34
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/* (RO) Secondary fault address for address space n, low word */
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#define AS_FAULTEXTRA_LO 0x38
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/* (RO) Secondary fault address for address space n, high word */
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#define AS_FAULTEXTRA_HI 0x3C
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/* End Register Offsets */
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#define GPU_IRQ_REG_ALL (GPU_IRQ_REG_COMMON)
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/*
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* MMU_IRQ_RAWSTAT register values. Values are valid also for
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* MMU_IRQ_CLEAR, MMU_IRQ_MASK, MMU_IRQ_STATUS registers.
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*/
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#define MMU_PAGE_FAULT_FLAGS 16
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/* Macros returning a bitmask to retrieve page fault or bus error flags from
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* MMU registers
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*/
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#define MMU_PAGE_FAULT(n) (1UL << (n))
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#define MMU_BUS_ERROR(n) (1UL << ((n) + MMU_PAGE_FAULT_FLAGS))
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/*
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* Begin AARCH64 MMU TRANSTAB register values
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*/
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#define MMU_HW_OUTA_BITS 40
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#define AS_TRANSTAB_BASE_MASK ((1ULL << MMU_HW_OUTA_BITS) - (1ULL << 4))
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/*
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* Begin MMU STATUS register values
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*/
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#define AS_STATUS_AS_ACTIVE 0x01
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#define AS_FAULTSTATUS_EXCEPTION_CODE_MASK (0x7<<3)
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#define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSLATION_FAULT (0x0<<3)
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#define AS_FAULTSTATUS_EXCEPTION_CODE_PERMISSION_FAULT (0x1<<3)
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#define AS_FAULTSTATUS_EXCEPTION_CODE_TRANSTAB_BUS_FAULT (0x2<<3)
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#define AS_FAULTSTATUS_EXCEPTION_CODE_ACCESS_FLAG (0x3<<3)
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#define AS_FAULTSTATUS_EXCEPTION_CODE_ADDRESS_SIZE_FAULT (0x4<<3)
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#define AS_FAULTSTATUS_EXCEPTION_CODE_MEMORY_ATTRIBUTES_FAULT (0x5<<3)
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#define AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT 0
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#define AS_FAULTSTATUS_EXCEPTION_TYPE_MASK (0xFF << AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
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#define AS_FAULTSTATUS_EXCEPTION_TYPE_GET(reg_val) \
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(((reg_val)&AS_FAULTSTATUS_EXCEPTION_TYPE_MASK) >> AS_FAULTSTATUS_EXCEPTION_TYPE_SHIFT)
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#define AS_FAULTSTATUS_EXCEPTION_TYPE_TRANSLATION_FAULT_0 0xC0
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#define AS_FAULTSTATUS_ACCESS_TYPE_SHIFT 8
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#define AS_FAULTSTATUS_ACCESS_TYPE_MASK (0x3 << AS_FAULTSTATUS_ACCESS_TYPE_SHIFT)
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#define AS_FAULTSTATUS_ACCESS_TYPE_GET(reg_val) \
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(((reg_val)&AS_FAULTSTATUS_ACCESS_TYPE_MASK) >> AS_FAULTSTATUS_ACCESS_TYPE_SHIFT)
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#define AS_FAULTSTATUS_ACCESS_TYPE_ATOMIC (0x0)
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#define AS_FAULTSTATUS_ACCESS_TYPE_EX (0x1)
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#define AS_FAULTSTATUS_ACCESS_TYPE_READ (0x2)
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#define AS_FAULTSTATUS_ACCESS_TYPE_WRITE (0x3)
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#define AS_FAULTSTATUS_SOURCE_ID_SHIFT 16
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#define AS_FAULTSTATUS_SOURCE_ID_MASK (0xFFFF << AS_FAULTSTATUS_SOURCE_ID_SHIFT)
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#define AS_FAULTSTATUS_SOURCE_ID_GET(reg_val) \
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(((reg_val)&AS_FAULTSTATUS_SOURCE_ID_MASK) >> AS_FAULTSTATUS_SOURCE_ID_SHIFT)
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#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT (0)
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#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK \
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((0xFF) << PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT)
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#define PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_GET(reg_val) \
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(((reg_val)&PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_MASK) >> \
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PRFCNT_FEATURES_COUNTER_BLOCK_SIZE_SHIFT)
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/*
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* Begin MMU TRANSCFG register values
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*/
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#define AS_TRANSCFG_ADRMODE_LEGACY 0
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#define AS_TRANSCFG_ADRMODE_UNMAPPED 1
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#define AS_TRANSCFG_ADRMODE_IDENTITY 2
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#define AS_TRANSCFG_ADRMODE_AARCH64_4K 6
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#define AS_TRANSCFG_ADRMODE_AARCH64_64K 8
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#define AS_TRANSCFG_ADRMODE_MASK 0xF
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/*
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* Begin TRANSCFG register values
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*/
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#define AS_TRANSCFG_PTW_MEMATTR_MASK (3ull << 24)
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#define AS_TRANSCFG_PTW_MEMATTR_NON_CACHEABLE (1ull << 24)
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#define AS_TRANSCFG_PTW_MEMATTR_WRITE_BACK (2ull << 24)
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#define AS_TRANSCFG_PTW_SH_MASK ((3ull << 28))
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#define AS_TRANSCFG_PTW_SH_OS (2ull << 28)
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#define AS_TRANSCFG_PTW_SH_IS (3ull << 28)
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#define AS_TRANSCFG_R_ALLOCATE (1ull << 30)
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/*
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* Begin Command Values
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*/
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/* AS_COMMAND register commands */
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#define AS_COMMAND_NOP 0x00 /* NOP Operation */
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#define AS_COMMAND_UPDATE 0x01 /* Broadcasts the values in AS_TRANSTAB and ASn_MEMATTR to all MMUs */
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#define AS_COMMAND_LOCK 0x02 /* Issue a lock region command to all MMUs */
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#define AS_COMMAND_UNLOCK 0x03 /* Issue a flush region command to all MMUs */
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/* Flush all L2 caches then issue a flush region command to all MMUs
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* (deprecated - only for use with T60x)
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*/
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#define AS_COMMAND_FLUSH 0x04
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/* Flush all L2 caches then issue a flush region command to all MMUs */
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#define AS_COMMAND_FLUSH_PT 0x04
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/* Wait for memory accesses to complete, flush all the L1s cache then flush all
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* L2 caches then issue a flush region command to all MMUs
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*/
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#define AS_COMMAND_FLUSH_MEM 0x05
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/* GPU_STATUS values */
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#define GPU_STATUS_PRFCNT_ACTIVE (1 << 2) /* Set if the performance counters are active. */
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#define GPU_STATUS_CYCLE_COUNT_ACTIVE (1 << 6) /* Set if the cycle counter is active. */
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#define GPU_STATUS_PROTECTED_MODE_ACTIVE (1 << 7) /* Set if protected mode is active */
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/* PRFCNT_CONFIG register values */
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#define PRFCNT_CONFIG_MODE_SHIFT 0 /* Counter mode position. */
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#define PRFCNT_CONFIG_AS_SHIFT 4 /* Address space bitmap position. */
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#define PRFCNT_CONFIG_SETSELECT_SHIFT 8 /* Set select position. */
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/* The performance counters are disabled. */
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#define PRFCNT_CONFIG_MODE_OFF 0
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/* The performance counters are enabled, but are only written out when a
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* PRFCNT_SAMPLE command is issued using the GPU_COMMAND register.
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*/
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#define PRFCNT_CONFIG_MODE_MANUAL 1
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/* The performance counters are enabled, and are written out each time a tile
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* finishes rendering.
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*/
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#define PRFCNT_CONFIG_MODE_TILE 2
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/* AS<n>_MEMATTR values from MMU_MEMATTR_STAGE1: */
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/* Use GPU implementation-defined caching policy. */
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#define AS_MEMATTR_IMPL_DEF_CACHE_POLICY 0x88ull
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/* The attribute set to force all resources to be cached. */
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#define AS_MEMATTR_FORCE_TO_CACHE_ALL 0x8Full
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/* Inner write-alloc cache setup, no outer caching */
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#define AS_MEMATTR_WRITE_ALLOC 0x8Dull
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/* Use GPU implementation-defined caching policy. */
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#define AS_MEMATTR_LPAE_IMPL_DEF_CACHE_POLICY 0x48ull
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/* The attribute set to force all resources to be cached. */
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#define AS_MEMATTR_LPAE_FORCE_TO_CACHE_ALL 0x4Full
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/* Inner write-alloc cache setup, no outer caching */
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#define AS_MEMATTR_LPAE_WRITE_ALLOC 0x4Dull
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/* Set to implementation defined, outer caching */
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#define AS_MEMATTR_LPAE_OUTER_IMPL_DEF 0x88ull
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/* Set to write back memory, outer caching */
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#define AS_MEMATTR_LPAE_OUTER_WA 0x8Dull
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/* There is no LPAE support for non-cacheable, since the memory type is always
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* write-back.
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* Marking this setting as reserved for LPAE
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*/
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#define AS_MEMATTR_LPAE_NON_CACHEABLE_RESERVED
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/* L2_MMU_CONFIG register */
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#define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT (23)
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#define L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY (0x1 << L2_MMU_CONFIG_ALLOW_SNOOP_DISPARITY_SHIFT)
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/* End L2_MMU_CONFIG register */
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/* THREAD_* registers */
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/* THREAD_FEATURES IMPLEMENTATION_TECHNOLOGY values */
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#define IMPLEMENTATION_UNSPECIFIED 0
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#define IMPLEMENTATION_SILICON 1
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#define IMPLEMENTATION_FPGA 2
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#define IMPLEMENTATION_MODEL 3
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/* Default values when registers are not supported by the implemented hardware */
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#define THREAD_MT_DEFAULT 256
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#define THREAD_MWS_DEFAULT 256
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#define THREAD_MBS_DEFAULT 256
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#define THREAD_MR_DEFAULT 1024
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#define THREAD_MTQ_DEFAULT 4
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#define THREAD_MTGS_DEFAULT 10
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/* End THREAD_* registers */
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/* SHADER_CONFIG register */
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#define SC_LS_ALLOW_ATTR_TYPES (1ul << 16)
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#define SC_TLS_HASH_ENABLE (1ul << 17)
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#define SC_LS_ATTR_CHECK_DISABLE (1ul << 18)
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#define SC_VAR_ALGORITHM (1ul << 29)
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/* End SHADER_CONFIG register */
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/* TILER_CONFIG register */
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#define TC_CLOCK_GATE_OVERRIDE (1ul << 0)
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/* End TILER_CONFIG register */
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/* L2_CONFIG register */
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#define L2_CONFIG_SIZE_SHIFT 16
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#define L2_CONFIG_SIZE_MASK (0xFFul << L2_CONFIG_SIZE_SHIFT)
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#define L2_CONFIG_HASH_SHIFT 24
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#define L2_CONFIG_HASH_MASK (0xFFul << L2_CONFIG_HASH_SHIFT)
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#define L2_CONFIG_ASN_HASH_ENABLE_SHIFT 24
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#define L2_CONFIG_ASN_HASH_ENABLE_MASK (1ul << L2_CONFIG_ASN_HASH_ENABLE_SHIFT)
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/* End L2_CONFIG register */
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/* IDVS_GROUP register */
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#define IDVS_GROUP_SIZE_SHIFT (16)
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#define IDVS_GROUP_MAX_SIZE (0x3F)
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#endif /* _UAPI_KBASE_GPU_REGMAP_H_ */
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