/*
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* [origin: Linux kernel drivers/watchdog/at91sam9_wdt.c]
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*
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* Watchdog driver for Atmel AT91SAM9x processors.
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*
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* Copyright (C) 2008 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
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* Copyright (C) 2008 Renaud CERRATO r.cerrato@til-technologies.fr
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* The Watchdog Timer Mode Register can be only written to once. If the
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* timeout need to be set from U-Boot, be sure that the bootstrap doesn't
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* write to this register. Inform Linux to it too
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*/
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#include <common.h>
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#include <watchdog.h>
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#include <asm/arch/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/at91_wdt.h>
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/*
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* AT91SAM9 watchdog runs a 12bit counter @ 256Hz,
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* use this to convert a watchdog
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* value from/to milliseconds.
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*/
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#define ms_to_ticks(t) (((t << 8) / 1000) - 1)
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#define ticks_to_ms(t) (((t + 1) * 1000) >> 8)
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/* Hardware timeout in seconds */
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#if !defined(CONFIG_AT91_HW_WDT_TIMEOUT)
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#define WDT_HW_TIMEOUT 2
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#else
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#define WDT_HW_TIMEOUT CONFIG_AT91_HW_WDT_TIMEOUT
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#endif
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/*
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* Set the watchdog time interval in 1/256Hz (write-once)
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* Counter is 12 bit.
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*/
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static int at91_wdt_settimeout(unsigned int timeout)
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{
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unsigned int reg;
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at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
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/* Check if disabled */
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if (readl(&wd->mr) & AT91_WDT_MR_WDDIS) {
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printf("sorry, watchdog is disabled\n");
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return -1;
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}
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/*
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* All counting occurs at SLOW_CLOCK / 128 = 256 Hz
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*
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* Since WDV is a 12-bit counter, the maximum period is
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* 4096 / 256 = 16 seconds.
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*/
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reg = AT91_WDT_MR_WDRSTEN /* causes watchdog reset */
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| AT91_WDT_MR_WDDBGHLT /* disabled in debug mode */
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| AT91_WDT_MR_WDD(0xfff) /* restart at any time */
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| AT91_WDT_MR_WDV(timeout); /* timer value */
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writel(reg, &wd->mr);
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return 0;
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}
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void hw_watchdog_reset(void)
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{
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at91_wdt_t *wd = (at91_wdt_t *) ATMEL_BASE_WDT;
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writel(AT91_WDT_CR_WDRSTT | AT91_WDT_CR_KEY, &wd->cr);
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}
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void hw_watchdog_init(void)
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{
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/* 16 seconds timer, resets enabled */
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at91_wdt_settimeout(ms_to_ticks(WDT_HW_TIMEOUT * 1000));
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}
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