/*
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* Copyright (c) 2017 Theobroma Systems Design und Consulting GmbH
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <dw_hdmi.h>
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#include <edid.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/grf_rk3399.h>
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#include <power/regulator.h>
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#include "rk_hdmi.h"
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static int rk3399_hdmi_enable(struct udevice *dev, int panel_bpp,
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const struct display_timing *edid)
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{
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
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int vop_id = uc_plat->source_id;
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struct rk3399_grf_regs *grf = priv->grf;
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/* select the hdmi encoder input data from our source_id */
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rk_clrsetreg(&grf->soc_con20, GRF_RK3399_HDMI_VOP_SEL_MASK,
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(vop_id == 1) ? GRF_RK3399_HDMI_VOP_SEL_L : 0);
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return dw_hdmi_enable(&priv->hdmi, edid);
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}
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static int rk3399_hdmi_ofdata_to_platdata(struct udevice *dev)
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{
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struct rk_hdmi_priv *priv = dev_get_priv(dev);
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struct dw_hdmi *hdmi = &priv->hdmi;
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hdmi->i2c_clk_high = 0x7a;
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hdmi->i2c_clk_low = 0x8d;
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return rk_hdmi_ofdata_to_platdata(dev);
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}
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static const char * const rk3399_regulator_names[] = {
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"vcc1v8_hdmi",
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"vcc0v9_hdmi"
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};
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static int rk3399_hdmi_probe(struct udevice *dev)
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{
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/* Enable regulators required for HDMI */
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rk_hdmi_probe_regulators(dev, rk3399_regulator_names,
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ARRAY_SIZE(rk3399_regulator_names));
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return rk_hdmi_probe(dev);
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}
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static const struct dm_display_ops rk3399_hdmi_ops = {
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.read_edid = rk_hdmi_read_edid,
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.enable = rk3399_hdmi_enable,
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};
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static const struct udevice_id rk3399_hdmi_ids[] = {
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{ .compatible = "rockchip,rk3399-dw-hdmi" },
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{ }
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};
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U_BOOT_DRIVER(rk3399_hdmi_rockchip) = {
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.name = "rk3399_hdmi_rockchip",
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.id = UCLASS_DISPLAY,
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.of_match = rk3399_hdmi_ids,
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.ops = &rk3399_hdmi_ops,
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.ofdata_to_platdata = rk3399_hdmi_ofdata_to_platdata,
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.probe = rk3399_hdmi_probe,
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.priv_auto_alloc_size = sizeof(struct rk_hdmi_priv),
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};
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