/*
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* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/addrspace.h>
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#include <asm/types.h>
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#include <mach/ar71xx_regs.h>
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#include <mach/ddr.h>
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#include <mach/ath79.h>
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#include <debug_uart.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifdef CONFIG_DEBUG_UART_BOARD_INIT
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void board_debug_uart_init(void)
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{
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void __iomem *regs;
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u32 val;
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regs = map_physmem(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE,
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MAP_NOCACHE);
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/*
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* GPIO9 as input, GPIO10 as output
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*/
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val = readl(regs + AR71XX_GPIO_REG_OE);
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val |= QCA953X_GPIO(9);
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val &= ~QCA953X_GPIO(10);
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writel(val, regs + AR71XX_GPIO_REG_OE);
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/*
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* Enable GPIO10 as UART0_SOUT
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*/
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val = readl(regs + QCA953X_GPIO_REG_OUT_FUNC2);
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val &= ~QCA953X_GPIO_MUX_MASK(16);
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val |= QCA953X_GPIO_OUT_MUX_UART0_SOUT << 16;
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writel(val, regs + QCA953X_GPIO_REG_OUT_FUNC2);
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/*
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* Enable GPIO9 as UART0_SIN
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*/
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val = readl(regs + QCA953X_GPIO_REG_IN_ENABLE0);
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val &= ~QCA953X_GPIO_MUX_MASK(8);
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val |= QCA953X_GPIO_IN_MUX_UART0_SIN << 8;
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writel(val, regs + QCA953X_GPIO_REG_IN_ENABLE0);
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/*
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* Enable GPIO10 output
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*/
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val = readl(regs + AR71XX_GPIO_REG_OUT);
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val |= QCA953X_GPIO(10);
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writel(val, regs + AR71XX_GPIO_REG_OUT);
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}
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#endif
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int board_early_init_f(void)
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{
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ddr_init();
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ath79_eth_reset();
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return 0;
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}
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